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Presenter

Xiaolong Guo
Kansas State University
Presentations
Networking
Work-in-Progress Poster
HADA: Leveraging Multi-Source Data to Train Large Language Models for Hardware Security Assertion Generation
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
DES5: Emerging Device and Interconnect Technologies
Research Manuscript
EVA: An Efficient and Versatile Generative Engine for Targeted Discovery of Novel Analog Circuits
4:15pm - 4:30pm PDT Tuesday, June 24 3003, Level 3
Design
DES4: Digital and Analog Circuits
Networking
Work-in-Progress Poster
Intelligence In The Fence: Construct A Privacy and Reliable Hardware Design Assistant LLM
6:00pm - 7:00pm PDT Sunday, June 22 Level 3 Lobby
DES5: Emerging Device and Interconnect Technologies
Research Manuscript
Hardware Generation with High Flexibility using Reinforcement Learning Enhanced LLMs
1:45pm - 2:00pm PDT Tuesday, June 24 3001, Level 3
AI
AI2: AI/ML Application and Infrastructure