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Presenter

Bei Yu
The Chinese University of Hong Kong
Presentations
Research Manuscript
DSPlacer: DSP Placement for FPGA-based CNN accelerator
10:30am - 10:45am PDT Wednesday, June 25 3006, Level 3
EDA
EDA7: Physical Design and Verification
Research Manuscript
LLMShare: Optimizing LLM Inference Serving with Hardware Architecture Exploration
1:45pm - 2:00pm PDT Tuesday, June 24 3002, Level 3
AI
AI4: AI/ML System and Platform Design
Research Manuscript
3D-Flow: Flow-based Standard Cell Legalization for 3D ICs
1:30pm - 1:45pm PDT Wednesday, June 25 3006, Level 3
EDA
EDA7: Physical Design and Verification
Research Manuscript
A Systematic Approach for Multi-Objective Double-Side Clock Tree Synthesis
2:15pm - 2:30pm PDT Wednesday, June 25 3006, Level 3
EDA
EDA7: Physical Design and Verification
Research Manuscript
From Flatland to Forest: Exploring Pareto-optimal Design through RTL Hierarchy Trees
5:00pm - 5:15pm PDT Tuesday, June 24 3004, Level 3
EDA
EDA1: Design Methodologies for System-on-Chip and 3D/2.5D System-in Package
Research Manuscript
Rank-based Multi-objective Approximate Logic Synthesis via Monte Carlo Tree Search
5:00pm - 5:15pm PDT Tuesday, June 24 3006, Level 3
EDA
EDA5: RTL/Logic Level and High-level Synthesis
Research Manuscript
MOSS: Multi-Modal Representation Learning on Sequential Circuits
11:00am - 11:15am PDT Wednesday, June 25 3000, Level 3
AI
AI2: AI/ML Application and Infrastructure
Research Manuscript
Curvilinear Optical Proximity Correction via Cardinal Spline
2:45pm - 3:00pm PDT Monday, June 23 3004, Level 3
EDA
EDA8: Design for Manufacturing and Reliability
Research Manuscript
SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation
11:30am - 11:45am PDT Wednesday, June 25 3003, Level 3
EDA
EDA8: Design for Manufacturing and Reliability