Session

DescriptionThis session explores cutting-edge advancements in hardware acceleration, focusing on optimizing computation, memory access, and parallelism in modern architectures. Featuring research on heterogeneous reconfigurable accelerators and FPGA optimization, the papers highlight novel approaches to accelerating key computational tasks. Topics include efficient sparse matrix multiplication, inter-tile parallelism, adaptive tree computations, large number modular reduction, compiler mapping strategies for CGRAs and physical design for nonvolatile FPGAs. Together, these works demonstrate how innovations in hardware and algorithm design are driving the future of high-performance computing, pushing the boundaries of speed, efficiency, and scalability in diverse applications.