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Research Manuscript: Exploring the Unchartered: From Chiplets to Architecture and Validation

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DescriptionWelcome to the session "Explore the Uncharted," diving into pioneering research that pushes the boundaries of system exploration, design and validation. This session brings together innovative approaches for multi-FPGA routing and design space exploration leveraging machine learning and AI to tailor system-on-chip (SoC) parameters to specific workloads; or optimizing multi-chiplet systems, focusing on cache hierarchies and inter-chiplet networks. The session offers validation methods for 3D integrated systems using physics-based multi-faceted simulation, novel Gem5-based accelerator integration opportunities, as well as speeding up ISS simulations through optimized instruction decoders.

Event TypeResearch Manuscript

TimeTuesday, June 243:30pm - 5:30pm PDT

Location3004, Level 3

Topics

Tracks

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Presentations

3:30pm - 3:45pm PDT	Gem5-AcceSys: Enabling System-Level Exploration of Standard Interconnects for Novel Accelerators Authors Qunyou Liu Marina Zapater David Atienza	EDA1: Design Methodologies for System-on-Chip and 3D/2.5D System-in Package
3:45pm - 4:00pm PDT	Adora Compiler: End-to-End Optimization for High-Efficiency Dataflow Acceleration and Task Pipelining on CGRAs Authors Jiahang Lou Qilong Zhu Yuan Dai Zewei Zhong Wenbo Yin Lingli Wang	EDA1: Design Methodologies for System-on-Chip and 3D/2.5D System-in Package
4:00pm - 4:15pm PDT	Automated Generation of Decoders for Irregular Instruction Sets Using Information-Theoretic Decision Trees Construction Algorithms Author Lillian Tadros	EDA1: Design Methodologies for System-on-Chip and 3D/2.5D System-in Package
4:15pm - 4:30pm PDT	Look Before You Leap: A Self-Review Bayesian Optimization Method for Constrained High-Dimensional Design Space Exploration Authors Xuyang Zhao Yiyang Zhao Zheng Wu Tianning Gao Zhaori Bi Changhao Yan Dian Zhou Xuan Zeng	EDA1: Design Methodologies for System-on-Chip and 3D/2.5D System-in Package
4:30pm - 4:45pm PDT	High-Performance Computing Architecture Exploration with Stage-Enhanced Bayesian Optimization Authors Vincent Fu Mohamed Benazouz Lilia Zaourar Alix Munier-Kordon	EDA1: Design Methodologies for System-on-Chip and 3D/2.5D System-in Package
4:45pm - 5:00pm PDT	On Design Space Exploration of Cache System in Multi-Chiplet Systems Authors Yan Zhang Xiaohang Wang Yingtao Jiang Amit Singh	EDA1: Design Methodologies for System-on-Chip and 3D/2.5D System-in Package
5:00pm - 5:15pm PDT	From Flatland to Forest: Exploring Pareto-optimal Design through RTL Hierarchy Trees Authors Donger Luo Qi Sun Xinheng Li Cheng Zhuo Bei Yu Hao Geng	EDA1: Design Methodologies for System-on-Chip and 3D/2.5D System-in Package
5:15pm - 5:30pm PDT	Synergistic Die-Level Router for Multi-FPGA System with Time-Division Multiplexing Optimization Authors Jiarui Wang Yanjing Liu Yibo Lin	EDA1: Design Methodologies for System-on-Chip and 3D/2.5D System-in Package

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