Session

DescriptionThis session explores innovative accelerator designs for AI and other applications, leveraging diverse technologies from ASICs and hardware-software co-design to FPGAs and Processing-in-Memory (PIM). The session begins with a cache-aware, multi-tenant DNN accelerator for NPUs. The next paper presents a FPGA-based configurable CAM architecture with multi-query support. Moving to PIM-based acceleration, the next paper explores a co-simulation environment for design space exploration of PIM architectures and Network-on-Chip (NoC) configurations, followed by a presentation on a novel PIM-based LLM accelerator. Next, a memory-efficient Fully Homomorphic Encryption (FHE) processing unit is presented. Finally, the session concludes with three presentations on specialized accelerators targeting vision and brain-computer interface applications.