Session

DescriptionThis session presents 6 exciting papers describing recent advances in high-level synthesis (HLS) and approximate computing. On the HLS front, four papers describe new contributions to HLS-generated asynchronous dataflow circuits; the generation of circuits that perform speculative execution efficiently; the use of multiple clock domains to reduce power; and, automated selection of kernels for hardware acceleration. The last two papers are related to approximate computing. The first of these automates design-space exploration in HLS to identify design points with high potential for area/power savings from approximation. The next introduces an efficient approach for binary-to-unary number conversion.