Session

DescriptionDespite decades of prior research in logic synthesis and optimization, the field continues to be highly active and progress continues unabated, as evidenced by the eight exciting papers in this session. The first two papers leverage the concept of equivalence graphs (e-graphs) for functional verification and reducing structural bias prior to technology mapping. The next four papers contribute to more traditional logic synthesis thrusts, including Boolean decomposition, logic restructuring, refactoring, and challenges associated with structural bias of the subject graph. The last two papers present innovations in approximate logic synthesis, and synthesis of optimal logic circuits.