Session
Squeezing Placement from FPGAs, Macros, Down to the Cell Level
DescriptionFrom block level to the transistor level, this session has placement for everyone. Learn about DSP placement for FPGA-based CNN acceleration, large scale macro placement, unified placement and routing, improved congestion modeling, and constructing the latest CFET standard cell libraries. Join us to explore the many facets of placement to optimize advanced-node semiconductor design.
Event Type
Research Manuscript
TimeWednesday, June 2510:30am - 12:00pm PDT
Location3006, Level 3
EDA
EDA7: Physical Design and Verification
Presentations
| 10:30am - 10:45am PDT | DSPlacer: DSP Placement for FPGA-based CNN accelerator | |
| 10:45am - 11:00am PDT | ReMaP: Macro Placement by Recursively Prototyping and Periphery-Guided Relocating | |
| 11:00am - 11:15am PDT | RUPlace: Optimizing Routability via Unified Placement and Routing Formulation | |
| 11:15am - 11:30am PDT | Differentiable Net-Moving and Local Congestion Mitigation for Routability-Driven Global Placement | |
| 11:30am - 11:45am PDT | Comprehensive Placement and Routing Framework with Guaranteed In-Cell Routability for Synthesizing Complementary-FET Cells | |
| 11:45am - 12:00pm PDT | Synthesis of CFET Cell Library Leveraging Backside Metal Routing |