Session

DescriptionThis session highlights advances in 3D IC design and clock tree synthesis (CTS) for improved power and performance. In 3D ICs, 3D-Flow minimizes legalization cell displacement using network flow; DCO-3D uses machine learning to predict and reduce routing congestion; while GNN-MLS mitigates congestion by routing across tiers with metal layer sharing, improving timing while addressing testability issues. For CTS, we explore approaches using front and back-side metal layers and reinforcement learning based "hub" node placement to minimize clock skew, buffering, and wire length. Finally, we look into a privacy-protecting, highly accurate federated learning framework to help advance the use of machine learning in EDA.