Session
Adventures in PCBs, Partitioning, and Legalization!
DescriptionBuckle up for an adventure through the realms of PCBs, partitioning, and legalization! Start by exploring novel algorithms for PCB global placement and legalization. Next, dive into a GNN-based graph partitioning algorithm, followed by a fast deterministic parallel hypergraph partitioner. Then, explore multi-height cell legalization with TSMC's recent FinFlex standard cells that allows for better PPA. End your journey with a detailed placer that optimizes secondary power delivery network for multi-power domain designs.
Event Type
Research Manuscript
TimeTuesday, June 2410:30am - 12:00pm PDT
Location3004, Level 3
EDA
EDA7: Physical Design and Verification
Presentations
| 10:30am - 10:45am PDT | Clearance-Constrained PCB Global Placement with Heterogeneous Components | |
| 10:45am - 11:00am PDT | Constraint Graph-based PCB Legalization Considering Dense, Heterogeneous, Irregular-Shaped, and Any-Oriented Components | |
| 11:00am - 11:15am PDT | GPart: A GNN-Enabled Multilevel Graph Partitioner | |
| 11:15am - 11:30am PDT | BlasPart: A Deterministic Parallel Partitioner for Balanced Large-Scale Hypergraph Partitioning | |
| 11:30am - 11:45am PDT | MIA-aware FinFlex Cell Legalization with Power-Driven Cell Version Substitution | |
| 11:45am - 12:00pm PDT | Secondary-Power-Cell-Aware Detailed Placement in Multiple Power Domain Designs |