Session
From Pixels to Chips: AI-Enhanced Layout & Mask Design
DescriptionThis session explores how Generative AI is revolutionizing semiconductor design, particularly in the realm of lithography and mask optimization. Discover how large vision models are enabling full-chip mask optimization and how self-supervised deep learning accelerates inverse lithography, pushing the boundaries of resolution and fidelity. We will showcase AI-driven pattern generation techniques for design rule compliance and explore the use of meta-learning to achieve generalizable hotspot detection. Learn how these approaches enable precision-aware yield optimization and ultimately, faster, more efficient chip design. Join us to witness the power of AI in next-generation DFM!
Event Type
Research Manuscript
TimeMonday, June 231:30pm - 3:00pm PDT
Location3004, Level 3
EDA
EDA8: Design for Manufacturing and Reliability
Presentations
| 1:30pm - 1:45pm PDT | LVM-MO: A Large Vision Model Pioneer for Full-Chip Mask Optimization* | |
| 1:45pm - 2:00pm PDT | SSDL-ILT: Efficient ILT utilizing a self-supervised deep learning model | |
| 2:00pm - 2:15pm PDT | PatternPaint: Practical Layout Pattern Generation Using Diffusion-Based Inpainting | |
| 2:15pm - 2:30pm PDT | Generalizable Lithographic Hotspot Detection Using Asynchronous Meta-Learning with Only One Shot | |
| 2:30pm - 2:45pm PDT | Accuracy Is Not Always We Need: Precision-aware Bayesian Yield Optimization | |
| 2:45pm - 3:00pm PDT | Curvilinear Optical Proximity Correction via Cardinal Spline |