Session
Welcome to the Silicon Rodeo: Wrangling Transistors, Taming Yield, and Riding the 3D Packaging Frontier
DescriptionReady for a wild ride through the next frontier of semiconductor design? From wrangling transistor layouts in CFET and Flip-FET to taming the unruly beasts of yield prediction with AI-driven multi-agent analysis, we’re corralling the toughest challenges in modern VLSI. We’ll dive into 3D chiplet packaging with YAP’s ultra-fast yield modeling, lasso post-exposure bake accuracy with SDM-PEB, and now, with ChipletEM, we’re putting the spurs to electromigration signoff in 2.5D and 3D integration. Saddle up as we rustle up the best innovations in chip design, ensuring your circuits don’t get bucked off the road to tape-out!
Event Type
Research Manuscript
TimeWednesday, June 2510:30am - 12:00pm PDT
Location3003, Level 3
EDA
EDA8: Design for Manufacturing and Reliability
Presentations
| 10:30am - 10:45am PDT | Mitigating Routability Problems in Complementary-FET-based VLSI Designs | |
| 10:45am - 11:00am PDT | Design and Technology Co-optimization Utilizing Flip-FET (FFET) Standard Cells | |
| 11:00am - 11:15am PDT | Multi-Agent Yield Analysis For Circuit Design | |
| 11:15am - 11:30am PDT | YAP: Yield Modeling and Simulation for Advanced Packaging | |
| 11:30am - 11:45am PDT | SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation | |
| 11:45am - 12:00pm PDT | ChipletEM: Physics-Based 2.5D and 3D Chiplet Integration Electromigration Signoff Tool Using Coupled Stress and Thermal Simulation |


