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Research Manuscript
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Welcome to the Silicon Rodeo: Wrangling Transistors, Taming Yield, and Riding the 3D Packaging Frontier
DescriptionReady for a wild ride through the next frontier of semiconductor design? From wrangling transistor layouts in CFET and Flip-FET to taming the unruly beasts of yield prediction with AI-driven multi-agent analysis, we’re corralling the toughest challenges in modern VLSI. We’ll dive into 3D chiplet packaging with YAP’s ultra-fast yield modeling, lasso post-exposure bake accuracy with SDM-PEB, and now, with ChipletEM, we’re putting the spurs to electromigration signoff in 2.5D and 3D integration. Saddle up as we rustle up the best innovations in chip design, ensuring your circuits don’t get bucked off the road to tape-out!
Event Type
Research Manuscript
TimeWednesday, June 2510:30am - 12:00pm PDT
Location3003, Level 3
Topics
EDA
Tracks
EDA8: Design for Manufacturing and Reliability