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Research Manuscript
:
Of Circuits and Secrets: Emerging Hardware Security Primitives and Cryptographic Accelerators
DescriptionWith the increasing complexity of modern hardware systems, ensuring robust security mechanisms is more critical than ever. This session on hardware security introduces emerging security primitives and cryptographic accelerators. The featured papers explore advancements in reliable physical fingerprint-based PUF designs and fluctuation sensing, hybrid verification techniques for hardware security, optimized authentication mechanisms for deep neural network (DNN) accelerators, and novel architectures for computing-in-memory (CIM)-based cryptographic accelerators.
Event Type
Research Manuscript
TimeWednesday, June 251:30pm - 3:00pm PDT
Location3008, Level 3
Topics
Security
Tracks
SEC2: Hardware Security: Primitives & Architecture, Design & Test
Presentations
1:30pm - 1:45pm PDTAcclMT: A Highly Resource-Efficient and Flexible Poseidon Hash-Based Merkle Tree Architecture
SEC2: Hardware Security: Primitives & Architecture, Design & Test
1:45pm - 2:00pm PDTLeakyDSP: Exploiting Digital Signal Processing Blocks to Sense Voltage Fluctuations in FPGAs
SEC2: Hardware Security: Primitives & Architecture, Design & Test
2:00pm - 2:15pm PDTFastPath: A Hybrid Approach for Efficient Hardware Security Verification
SEC2: Hardware Security: Primitives & Architecture, Design & Test
2:15pm - 2:30pm PDTRe4PUF: A Reliable, Reconfigurable ReRAM-based PUF Resilient to DNN and Side Channel Attacks
SEC2: Hardware Security: Primitives & Architecture, Design & Test
2:30pm - 2:45pm PDTACIM-QMM: Efficient Analog Computing-in-Memory Accelerator for QC-MDPC McEliece Cryptosystem
SEC2: Hardware Security: Primitives & Architecture, Design & Test
2:45pm - 3:00pm PDTAutoSkewBMT: Autonomously Synthesizing Optimized Integrity Authentication Mechanism for DNN Accelerators
SEC2: Hardware Security: Primitives & Architecture, Design & Test