Session
All Quiet on the Processor Front: Next-Gen Processor Security and Enclave Innovations
DescriptionAs computing systems become increasingly complex, securing CPUs and enclave-based architectures remains a top priority. This hardware security session showcases cutting-edge research on security primitives and architectural enhancements for these critical systems. The selected papers explore fuzzing-based techniques for identifying critical CPU vulnerabilities, propose practical solutions for secure virtual machine architectures, analyze security assets in System-on-Chip (SoC) designs, and extend TrustZone technology to heterogeneous FPGA architectures.
Event Type
Research Manuscript
TimeMonday, June 2310:30am - 12:00pm PDT
Location3008, Level 3
Security
SEC2: Hardware Security: Primitives & Architecture, Design & Test
Presentations
| 10:30am - 10:45am PDT | IntraFuzz: Coverage-Guided Intra-Enclave Fuzzing for Intel SGX Applications | |
| 10:45am - 11:00am PDT | BPUFuzzer: Effective Fuzz Testing for Branching Transient Execution Vulnerabilities of RISC-V CPU | |
| 11:00am - 11:15am PDT | ADVeRL-ELF: ADVersarial ELF Malware Generation using Reinforcement Learning | |
| 11:15am - 11:30am PDT | Identifying System-on-Chip Security Assets with Structure-Based Analysis | |
| 11:30am - 11:45am PDT | Zion: A Practical Confidential Virtual Machine Architecture on Commodity RISC-V Processors | |
| 11:45am - 12:00pm PDT | FPGA-TrustZone: Security Extension of TrustZone to FPGA for SoC-FPGA Heterogeneous Architecture |