Session
Watt's Next: Low-Power Design and Verification Trends
Session Chair
DescriptionAccurate power analysis is crucial for designing power-optimized silicon, especially as modern applications demand higher performance within stringent power and thermal constraints. In this session, presenters will share their experiences and insights into advanced power analysis techniques and optimization strategies across a wide range of applications.
Event TypeEngineering Presentation
TimeTuesday, June 2410:30am - 12:00pm PDT
Location2010, Level 2
Front-End Design
Chiplet
Presentations
| 10:30am - 10:45am PDT | Streamlining Low Power Verification for Multi-die SoCs: A Comprehensive Framework | |
| 10:45am - 11:00am PDT | UPF Guided Design Editing for Early Low Power Verification Sign Off | |
| 11:00am - 11:15am PDT | Enhancing RTL Power Accuracy with Advanced Buffer Modeling for Improved Efficiency and Correlation | |
| 11:15am - 11:30am PDT | Unveiling the Core Truth: Advanced Glitch Power Analysis and Optimization Using Statistical Methodology | |
| 11:30am - 11:45am PDT | A Novel approach for workload based GPU datapath power optimization | |
| 11:45am - 12:00pm PDT | Optimal Power Estimation Methodology for CXL Memory Controllers |