Session
Verification Innovation: Shaping the Future of Design Validation
DescriptionJoin us to learn about new strategies in the catch-up game verification engineers play daily with the increasing design complexity and tighter schedules. In this session, presenters will talk about advanced verification techniques spanning from RTL to GLS covering Python, UVM and SystemC driven solutions.
Event TypeEngineering Presentation
TimeWednesday, June 2510:30am - 12:00pm PDT
Location2008, Level 2
Front-End Design
Presentations
| 10:30am - 10:45am PDT | Refresh your UVM Testbench with a Spritz of Python | |
| 10:45am - 11:00am PDT | AACT: Automated Analog Coverage Tool for Mixed Signal Verification | |
| 11:00am - 11:15am PDT | AUTOLNKGEN: Automated Random Linker File Generation Framework for Heterogenous SoC Verification & Validation | |
| 11:15am - 11:30am PDT | Efficient Hardware Fuzzing based on SystemC | |
| 11:30am - 11:45am PDT | Netlist Powered Emulation Paradigm: Pioneering Breakthroughs in Gate Level Verification | |
| 11:45am - 12:00pm PDT | Enhancing Verification Efficiency with Garbage-Model Methodology |