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Engineering Presentation
: Formal and Static Verification: Stop Bugs Before They Think They're Invited
Session Chair
Vikas Sachdeva
Real Intent
DescriptionStatic and formal based flows/solutions provide a bottom-up verification approach, helping engineers find certain class of bugs in the shortest time and helping manage efficient distribution of load across all verification technologies. In this session, presenters will share their experiences on applications like data path validation, formal verification, and metastability analysis (CDC/RDC).
Event Type
Engineering Presentation
TimeTuesday, June 241:30pm - 3:00pm PDT
Location2010, Level 2
Topics
Front-End Design
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