Session
IP Gold – New Digital Design Nuggets
Session Chair
DescriptionThis session presents six interesting digital IP components and design techniques. It covers resilience against side channel attacks in encryption IP as well as new blocks addressing the need for communication protocols, low power clocks, decimation cores and vector floating point math units.
Event Type
Engineering Presentation
TimeWednesday, June 2510:30am - 12:00pm PDT
Location2010, Level 2
IP
Presentations
| 10:30am - 10:45am PDT | Balancing Performance and Side-Channel Resilience in a Lightweight ECC Cryptosystem | |
| 10:45am - 11:00am PDT | Simulation-based Pre-Silicon Side-Channel Analysis of AES-GCM | |
| 11:00am - 11:15am PDT | Energy Efficient I3C IP Subsystem for Low Power IoT | |
| 11:15am - 11:30am PDT | Hybrid and Adaptive Digital Filter architecture for Robust tracking of On-chip Low Frequency Oscillator Period, enabling Crystal less BLE operation in Low Power Wireless MCUs | |
| 11:30am - 11:45am PDT | High Figure of Merit Polyphase Decimation Core IP | |
| 11:45am - 12:00pm PDT | Reconfigurable Vector Floating Point Accelerator on FPGAs |


