Session
Arrival Pathways for Crossing the Chip-n-Package Routes
Session Chair
DescriptionLearn the routing strategies to cross the maze of chip to packaged parts delivery - keeping the clocks aligned to finding ways around crowded area or feeding throughs that cut the walls. Get Set and GO!
Event Type
Engineering Presentation
TimeTuesday, June 241:30pm - 3:00pm PDT
Location2012, Level 2
AI
Back-End Design
Presentations
| 1:30pm - 1:45pm PDT | A Novel Feedthrough Insertion Methodology for Hierarchical SOC Designs: Achieving Reduction in Die Area | |
| 1:45pm - 2:00pm PDT | ML based PPA Push using XAI | |
| 2:00pm - 2:15pm PDT | Routing Congestion Mitigation Techniques Targeting Dense Designs | |
| 2:15pm - 2:30pm PDT | Efficient Automation Strategy for Package Substrate Routing | |
| 2:30pm - 2:45pm PDT | Deterministic On Chip Variation Modeling of Clock Mesh | |
| 2:45pm - 3:00pm PDT | Dynamic Optimization of Skew Balancing through an Innovative Correct-by-Construct Path Delay Query Technique |