Session
Complete Your Power and Thermal Envelopes with Security and Predictability
Session Chair
DescriptionKeep your cool while removing heat and not revealing your secrets to performance and security. This season deliver secure designs that don't melt down.
Event Type
Engineering Presentation
TimeTuesday, June 243:30pm - 5:00pm PDT
Location2012, Level 2
Back-End Design
Chiplet
Presentations
| 3:30pm - 3:48pm PDT | A Hybrid Simulation Technique for High-Speed and Accurate System-Level Side-Channel Leakage Analysis | |
| 3:48pm - 4:06pm PDT | 3DIC Thermal-Aware Early Design Optimization | |
| 4:06pm - 4:24pm PDT | Mitigation of Functional Power Dissipation in Parasitic Scan Shift Test Buffers | |
| 4:24pm - 4:42pm PDT | PPA Evaluation of BS-PDN Compared to FS-PDN in the Early Stage | |
| 4:42pm - 5:00pm PDT | A Simulation Technique of Thermal Side-Channels from Cryptographic Circuits |