Session

DescriptionStructural testing has been very successful in the VLSI manufacturing process to screen out faulty devices and provide high outgoing product quality. However, recent reported data from Google and Meta show that faulty chips are escaping the test programs and ending in causing serious trouble in field; e.g., Silent Data Corruptions (SDC). Meta recently reported at International Test Conference 2024 that approximately 78% of in field interruptions are attributed to confirmed hardware issues such faulty GPUs, faulty memories, etc. This calls for immediate improvements of used fault models and test patterns at manufacturing test.

This session addresses the limitations of existing fault models and test generation, and highlights further direction for better fault modelling; both for logic and memory. The first talk shows the limitations of (commercial) existing solutions. For example, reliance on the stuck-at fault model persists even though data extracted from the test literature reveals that the percentage of defects that exhibit stuck-at fault behaviour has significantly reduced over the years; real data measurements will be provided to support statement. The second talk shows how increasing random process variations in advanced low-nanometer nodes are introducing timing marginalities that can cause unpredictable failures under adverse operating conditions; such marginalities are not considered during test generation for structural manufacturing tests yet. Consequently it is not detected by currently used industrial test programs leading to a significant number of test escapes. The third talk presents Device-Aware-Test; a new approach that aims at closing the gap between fault models and real defects. The approach is demonstrated on an industrial STT-MRAM design.