Session

DescriptionAs monolithic chips face technological and practical barriers, 2.5D/3D integration of predesigned chiplets is emerging as a key approach to continuously scale up processor performance, improve energy efficiency, enhance IP reuse at reduced cost, and expedite time-to-market. Such a paradigm shift requires a tight collaboration between packaging and chiplet designs throughout the entire design cycle, including technology, circuits, architectures and design automation tools. Designers must develop innovative 3D modules and chiplet interfaces, while evaluating physical and system-level tradeoffs in performance, data movement and energy efficiency. In addition, design and synthesis tools need to incorporate 3D integration and planning knowledge to enable seamless packaging and chiplet co-design. All these requirements pose substantial challenges to today's isolated ASIC and package design processes.
This special session features three visionary talks by industry and academic leaders, highlighting the essential research priorities for chiplet-packaging co-design. These talks delve into the technological foundations, state-of-the-art design methodologies for heterogeneous chiplets, emerging chiplet standards and IPs, and the pressing needs for simulation and design automation tools. Advances in this field will promote tight collaboration between chiplet and package designs, helping shed light on both the challenges and the vast potential of heterogeneous integration.