Session Full Program · Contributors · Organizations · Search Program · Flagged · Happening NowMore…Search ProgramFlaggedHappening NowNetworking, Work-in-Progress Poster: Sunday Work-in-Progress Poster ReceptionEvent TypeNetworking, Work-in-Progress PosterTimeSunday, June 226:00pm - 7:00pm PDTLocationLevel 3 LobbySimilar SessionsSpike It, See It, Say It: Next-Gen AI ProcessingStorage Meets Computing Power for Advancing AI and Data Processing EfficiencyBreaking Barriers: Compute-in-Memory for Transformer AccelerationPresentations3D-IC Stacking and Floorplan Design Methodology through ML-based Pre-trained Model and Practical Macro Placement Framework for Performance and Thermal Co-optimizationAuthorsYu-Wei TsengPo-Hsiang HuangWei-Yi Willy HuA Fast and Accurate Thermal Solver for Chip Thermal Throttling AnalysisAuthorsShinyu ShiauSainan LuStimit ShahXin AiYun DaiA Retina-Inspired Pathway to Real-Time Motion Prediction inside Image Sensors for Extreme-Edge IntelligenceAuthorsSubhradip ChakrabortyShay SnyderMd KaiserMaryam ParsaGregory SchwartzAkhilesh JaiswalA Scalable Two-Step Approach to Optimize Data and Energy Migrations in Mini Data Centers for Carbon-Neutral ComputingAuthorsKazuki OkazawaHiroki NishikawaDafang ZhaoIttetsu TaniguchiTakao OnoyeMarcos da SilvaAbdoulaye GamatieA Graph-Based Approach for Optimizing Pin Access in Nanosheet FET Standard Cell Library SynthesisAuthorsMeng-Yu ShihYih-Lang LiAccelerating Clustering Algorithms for Large-Scale Datasets via Collaborative GPU and CXL-Memory ArchitectureAuthorsTaehyung ParkHyuk-Jae LeeChae Eun RheeAccelerating device level synthesis of binarized convolutional neural networksAuthorsFrancisco Andreo-OliverGines Domenech-AsensiJose Diaz-MadridRamon Ruiz-MerinoAdaMAP: Adaptive Hardware Mapping for Model Compression using Low-Rank DecompositionAuthorsPriyansh BhatnagarRishabh KumarPranav RajMingu KangAdora: An Arithmetic and Dynamic Operation Reconfigurable Accelerator using In-Memory Look-Up TablesAuthorsStefan MaczynskiPurab SutradharMark IndovinaSathwika BavikadiSai Manoj Pudukotai DinakarraoAmlan GangulyAI-enabled Efficient Extraction of Entire Advanced IC PackageAuthorsXiaoyan XiongYingxin SunJiyue ZhuGang KangJian LiuAlphaSparseTensor: Discovering Faster Sparse Matrix Multiplication Algorithms on GPU for LLM inferenceAuthorsXuanzheng WangShuo MiaoZihan ZhuPeng QuYouhui ZhangAn Advanced Wait-Free Protocol for Data Communication and Consistency in Multi-Core Real-Time Embedded SystemsAuthorsDong LiSen WangAdhip ShuklaYuchen ZhouKhaja ShazzadHaibo ZengApproximation-based Inter-PE Communication-free Image Filtering for Commodity PIMAuthorsChan LeeShinnung JeongHeelim ChoiJaeho LeeHaeeun JeongHoyun YoumJu Min LeeHanjun KimAutomated Hardware-Mapping Co-Design for Neural Network Acceleration with Single-Step Reinforcement LearningAuthorsYifeng XiaoYurong XuNing YanMasood MortazaviPierluigi NuzzoAutomating RTL generation using Agentic LLMsAuthorsAthmanarayanan Lakshmi NarayananMahesh SubedarOmesh TickooAutomotive Remote Direct Memory Access (ARDMA) for Software Defined Vehicle (SDV)AuthorsNithya SomanathBhagyashri KattiZachary SteigerwaldKhaja ShazzadMarkus JochimYuchen ZhouSteve DiBellaBank-Split PIM: Enabling Concurrent PIM and Memory Operations for LLM Inference in Heterogeneous SystemsAuthorsHyeongjun ChoYoonho JangSeokin HongBeyond Verilog: Agents for Emerging HDLsAuthorsFARZANEH RABIEI KASHANAKIMark ZakharovJose RenauBlaqsmith: Resolving Two-Qubit Gate Count Explosion in T-Count-Optimized Quantum CircuitsAuthorsMu-Te LauHsiang-Chun YangHsin-Yu ChenChung-Yang (Ric) HuangCarbonSet: A Dataset to Analyze Trends and Benchmark the Sustainability of CPUs and GPUsAuthorsJiajun HUChetan Choppali SudarshanMaxwell CliffordVidya A. ChhabriaAman AroraCiS: In-Storage Compression for Improving Read Performance of NAND Flash-based SSDsAuthorsMinjin ParkMinkyu ChoiSeongwook KimJunbum ParkJOONSEONG HWANGSeokin HongCombining Physics-Informed and Data-Driven Learning for Efficient Modeling of Memristive DevicesAuthorsZihan ZhangMarco DonatoDES5: Emerging Device and Interconnect TechnologiesDaedalus: a Floorplanning Strategy for Next-Generation 3D Chiplet IntegrationAuthorsSebastiano GaiardelliMichele LoraMarco CignarellaAnna FontanelliFrancesco RossiMichele TaliercioFranco FummiDeep co-design of a 7.461 TOPS/W/mm^(2) CGRA for Edge-based Perception applicationsAuthorsRohit PrasadPascal AubryTiana RAKOTOVAOKods TrabelsiDesign guidelines of succinct pulse generators for scalable superconducting qubit controllersAuthorsRyosuke MatsuoKazuhisa OgawaHidehisa ShiomiMakoto NegoroRyutaro OhiraTakefumi MiyoshiMichihiro ShintaniHiromitsu AwanoTakashi SatoJun ShiomiDesign-Aware Multi-Armed Bandit Approach for Automated Design VerificationAuthorsLorenzo FerrettiSurya BandlamudiNihar AthreyasVikram NarayanSamir MittalDesigning and Evaluating HBM-aware NTT AcceleratorAuthorsSangwon ShinSon PhamLei XuWeidong ShiTaeweon SuhDualMap: Enhancing Efficiency for In Memory Computing with Dual Strategies of Kernel Duplication and CompactionAuthorsWenxin WangMeng PangPeng QuYouhui ZhangDynamic FPGA Acceleration for Cloud Workloads: A HLS-based JIT Compilation ApproachAuthorsRui LiShuang CaoEfficiently Exploiting Inference Parallelism in Two-Sided Sparse CNNs for a High-Speed, Low-Cost AcceleratorAuthorsSon PhamSangwon ShinLei XuWeidong ShiTaeweon SuhEHPC: Efficient Heterogeneous Probabilistic Computing Architecture for Floorplanning AccelerationAuthorsWeican ChenChenhao XiaGuanwen YaoHaoxuan WangFei LiuEMSTrans: An Efficient Hardware Accelerator for Transformer with Multi-Level Sparsity AwarenessAuthorsDingyang ZouBaichen ChenQiye DingLiang XuMeiqi WangZhongfeng WangEnabling Systolic Computing on Elastic Coarse-Grained Reconfigurable Array for HPC and AIAuthorsChenlin ShiBoma AdhiLin TengShinobu MiwaKentaro SanoEqBaB: Efficient Equivalence Verification for Compressed DNNs with Bound PropagationAuthorszihao moyejiang yangweiming xiangExtending RISC-V based GPGPU for fast execution of regular data-intensive kernelsAuthorsGiuseppe SardaNimish ShahAbubakr NadaDebjyoti BhattacharjeeMarian VerhelstFast Simulation Algorithm for Negative-Capacitance FinFET Based on Latency Insertion MethodAuthorsYi ZhouJosé Schutt-AinéFlowGuard: Towards Reliable DNN Accelerators via Fine-Grained Fault Tolerance in Systolic ArrayAuthorsSihyung KimGwangeun ByeonSeongwook KimJunbum ParkSeokin HongGAIA: A Generative AI Approach for Enabling Aircraft Digital Twin CreationAuthorsFrancesco BiondaniLuigi CapogrossoNicola Dall'OraEnrico FraccaroliDomenico MiglioreFrancesco AcerraMarco CristaniFranco FummiGenerator of constrained test pattern based on multi-scale gradient generative adversarial networksAuthorsYajuan SuTianyang GaiYuqin WangXiaojing SuXin HongPengyu RenYujie JiangYayi WeiGraCo - A Graph Composer for Integrated CircuitsAuthorsStefan UhlichAndrea BonettiArun VenkitaramanAli MomeniRyoga MatsuoChia-Yu HsiehEisaku OhbuchiLorenzo ServadeiGraphDTA: Fast Dynamic Timing Analysis for Circuits with Graph Representation LearningAuthorsGuangxi FanTianliang MaXuguang SunXun WangXiaolei ZhuZhiping YuLeilai ShaoGraphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator GenerationAuthorsXinmiao ZhangZheng FengShengwen LiangXinyu ChenCheng LiuLei ZhangHuawei LiXiaowei LiGRL: Redesign Distributed Reinforcement Learning Training on One GPUAuthorsZhikuang XinZhenghong WuRongqiang Caohaoyu WangHaisha ZhaoJue WangYangang WangHADA: Leveraging Multi-Source Data to Train Large Language Models for Hardware Security Assertion GenerationAuthorsWeimin FuYiting WangZelin LuYifang ZhaoXiaolong GuoGang QuHeadTile: A Scalable and Efficient Accelerator for Large Language Model Inference with 3D Memory IntegrationAuthorsQingshan XueYihao ShiXueyi ZhangBo WangShengbai LuoYunping ZhaoSheng MaTiejun LiHigh-Level Acceleration of Quantum Simulation Frameworks on Reconfigurable HardwareAuthorsFNU PratibhaVinayak JhaIshraq IslamAnshul MauryaManu ChaudharyAlvir NobelKieran EganNaveed MahmudEsam El-ArabyHIVE: A Hierarchical Inverse Graph Construction Framework for Verilog Code Generation and Compilation Error Correction Using Large Language ModelsAuthorsQingchen ZhaiFrank QuHao YuCharles YoungLING LIANGZhiwei ZhangTao XieYuan XieHyDra: SOT-CAM Based Vector Symbolic Macro for Hyperdimensional ComputingAuthorsMd Mizanur Rahaman NayanChe-Kai LiuZishen WanArijit RaychowdhuryAzad NaeemiI-PIM: Indirect Address Hashing for Efficient Processing-In-Memory on GPUAuthorsGyubeom JeonJiho KimZhixian JinJangpyo LeeHyojun SonJohn KimIM-DSE: Intelligent Muti-target Design Space Exploration for BNN Accelerators in FPGAsAuthorsQianyi ChenLu WangXia ZhaoGuangda ZhangHuadong DaiIntelligence In The Fence: Construct A Privacy and Reliable Hardware Design Assistant LLMAuthorsShijie LiWeimin FuYifang ZhaoXiaolong GuoYier JinInvestigating Security Breaches in Vehicle Infotainment SystemsAuthorsYingjie CaoMinrui YanGeorge CraneDean SullivanYa-Long GuoHaoqi ShanXiapu LuoLightCROSS: A Secure and Memory Optimized Post-Quantum Digital Signature CROSSAuthorsPuja MondalSuparna KunduSupriya AdhikaryAngshuman KarmakarLLM-based Soft Error tolerant Design for DNN acceleratorsAuthorsYihao ShiQingshan XueLuo shengbaiTiejun LieSheng MaLPA-NTT: Efficient Lightweight Polynomial Multiplication Accelerator with Hybrid NTT AlgorithmAuthorsSizhao LiWenqi ZhangTiantai DengKaiyuan YangXing HuangMemSearch: An Efficient Memristive In-memory Search Engine with Configurable Similarity MeasuresAuthorsYingjie YuHouji ZhouJiancong LiTong HuJia ChenYi LiXiangshui MiaoMERINDA: Model Recovery in FPGA based Dynamic ArchitectureAuthorsBin XuAyan BanerjeeSandeep GuptaMitigating Resource Contention for Responsive On-device Machine Learning InferencesAuthorsMinsung KimJihoon LeeSeongjin ChouWhisoo ChungWoosung KangHyosu KimSangeun OhHoon Sung ChwaKilho LeeMOOPSE: Leveraging High-Radix Booth Encoders for Area-Efficient Matrix Multiply OperationsAuthorsChenlin ShiToru KoizumiRyota ShioyaHayato YamakiHiroki HondaShinobu MiwaMPE : A Power-Efficient Edge-Device Mamba Processor with Multi-Dimensional Calculation-Compression SchemeAuthorsZhou WangHaochen DuXiaonan TangShushan QiaoShouyi YinAnil BharathManos DrakakisMTrace : Trusted logging using ARM DWT on embedded devicesAuthorsDong Kyun YangSeyoung BaikSangwook LeeJinsoo JangNLS: Natural-Level Synthesis for Hardware Implementation Through GenAIAuthorsKaiyuan YangXinyi WangHuang OuyangBingjie LuYanbo WangCharith AbhayaratneSizhao LiLong JinTiantai DengOpenAssert: Towards Open-Source Large Language Models for Assertion GenerationAuthorsAnand MenonSamit MiftahAmisha SrivastavaShamik KunduArnab RahaSouvik KunduSuvadeep BanerjeeDeepak MathaikuttyKanad BasuOpenGC: An Open-Source Gain Cell CompilerAuthorsXinxin WangLixian YanShuhan LiuLuke UptonShengman LiJesse Cirimelli-LowMatthew GuthausH.-S. WongDES5: Emerging Device and Interconnect TechnologiesOpti-SpiSSL: A Highly Reconfigurable Hardware Generation Framework for Spiking Self-Supervised Learning on Heterogeneous SoCAuthorsHeuijee YunDaejin ParkOT-CRL: Online Tuning of DRAM Controllers Using Continual Reinforcement LearningAuthoryen hao huangPECA: Polyhedral-Based Efficient Compiler for AI Applications on CGRAsAuthorsMingyang KouWeiqing JiShouyi YINHailong YaoPiano: A Multi-Constraint Pin Assignment-Aware FloorplannerAuthorsZhexuan XuKexin ZhouJie WangZijie GengSiyuan XuShixiong KaiMingxuan YuanFeng WuProCamo: A Fast Post-Manufacturing Programmable Camouflaged Logic Family Resilient to DPA Attack and Reverse EngineeringAuthorsSeo Hyun KimMinhyeok JeongJongmin LeeReVEAL: Reverse Engineering of Multiplier Architectures via Graph Learning for Computer Algebra VerificationAuthorsChen ChenDaniela KaufmannChenhui DengCunxi YuSafeSSD: Treeless SSD Protection by Leveraging Physical Address as Version NumberAuthorsTalha AhmedSeokin HongSayram: A Hardware-software Co-design to Accelerate Wireless Baseband ProcessingAuthorsXinbing ZhouShaobo ShiShaohan LiuPeng HaoYunxiang TangYi ManDake LiuScalable Framework for Traffic Rule Enforcement in Autonomous Driving: Evaluating Adaptability Across Edge PlatformsAuthorsFatima IdreesNarmada AmbigapathyPeer AdeltCharles SteinmetzAchim RettbergScalar RunaheadAuthorsDean YouJieyu JiangXiaoxuan WangYushu DuZhihang TanWenbo XuHui WangJiapeng GuanShuai ZhaoRan WeiZhe JiangSchemato - An LLM for Netlist-to-Schematic ConversionAuthorsRyoga MatsuoStefan UhlichArun VenkitaramanAndrea BonettiChia-Yu HsiehAli MomeniLukas MauchAugusto CaponeEisaku OhbuchiLorenzo ServadeiSCMG: Scalable and Configurable FPGA-based Multiplier Generator using Integer Linear ProgrammingAuthorsYao ShangshangZhu JunyiLang QingjieWang RuoxiShen LiSecONN: An Optical Neural Network Framework with Concurrent Detection of Thermal Fault Injection AttacksAuthorsKota NishidaYoshihiro MidohNoriyuki MiuraSatoshi KawakamiJun ShiomiDES5: Emerging Device and Interconnect TechnologiesSOFTONIC: A Photonic Design Approach to SoftMax Activation for High-Speed Analog AI AccelerationAuthorsPRIYABRATA DASHAnxiao JiangDharanidhar DangSolving Multidimensional Partial Differential Equations on Quantum HardwareAuthorsManu ChaudharyKareem El-ArabyAlvir NobelVinayak JhaDylan KneidelIshraq IslamEsam El-ArabySpeeding Up Global Placement Method by Integrating a Precorrected FFT SolverAuthorsHangyu ZhangSachin S. SapatnekarSqueezing Out Hidden Margins for Hard-to-Solved IR Violations in VLSI by Extracting Timing Slack MethodologyAuthorsYu-Wen LinWei-Chih HsiehFlorentin DartuSwiftMax: Reducing Training Time for Learnable Softmax Alternative in Customized AccelerationAuthorsHaoxiang SunYiqi LiuWenbo ZhangZhenshan BaoSynAlign: Annotating HDLs with Synthesis ResultsAuthorsSakshi GargJose RenauTEA-GNN: Technology Node Exploration Acceleration via End-of-Flow Metric PredictionAuthorsLuis Humberto Pena TrevinoLirida NavinerFady AbouzeidPhilippe RocheTickTockStack: In-Datapath Current Imbalance Elimination Using Clocked Differential Logic in a Voltage Stacked Vector ProcessorAuthorsMichał GorywodaWanyeong JungTiLeR: Hardware-In-The-Loop Mitigation of Software Timing Side-Channel VulnerabilitiesAuthorsTasneem SuhaRima AwadPrabuddha ChakrabortyTSO: Boosting Rematerialization Training via Optimal Tensor Scheduling OptimizationAuthorsYu TangLujia YinQiao LiCheng LiLinbo QiaoWujun WenHengjie LiXingcheng ZhangDongsheng LiUnary Positional System: Flexible Balance of Hardware Area and PerformanceAuthorsZeshi LiuZheng WengHaihang YouUnleashing the Potential of Hyperdimensional Computing on Skyrmion Racetrack MemoriesAuthorsYu-Pei LiangJian-Yi PanYen-Ting ChenWei-Kuan ShihYuan-Hao ChangEarly Mismatch Detection in Analog Layout Using PLS NetlistAuthorsAbhishek JainAshutosh SinghAnil KumarKrish SinghMultiple Row Buffer DRAMAuthorsK. ChitraArjun DeyAryabartta SahuMinesh PatelLeveraging Artificial Neural Networks for Accurate and Efficient Glitch Propagation ModelingAuthorsAnastasis VagenisDimitrios GaryfallouGeorge Stamoulis
