Session Full Program · Contributors · Organizations · Search Program · Flagged · Happening NowMore…Search ProgramFlaggedHappening NowNetworking, Work-in-Progress Poster: Monday Work-in-Progress Poster ReceptionEvent TypeNetworking, Work-in-Progress PosterTimeMonday, June 236:00pm - 7:00pm PDTLocationLevel 2 LobbySimilar SessionsSmart Circuits, Smarter Algorithms: AI-Driven Innovations in Circuit Modeling and OptimizationFaster, Safer, Greener: AI-driven Evolution in Smart EdgeAI Meets Silicon: Transforming Hardware Design through AI-Driven InnovationPresentationsA Novel Multi-Node-Upset Recoverability Verification Method with Generalized Model for Radiation-Hardened LatchesAuthorsAibin YanYongkang XuWangjin JiangZhengfeng HuangTianming NiXiaoqing WenPatrick GirardXiaoming ChenA Novel Power-gradient-aware Cell Placement Methodology Considering 3D-IC Stacking Thermal Boundary to Achieve Timing and Thermal Co-optimizationAuthorsChien-Chih HuangMing-Chuan HuPo-Hsiang HuangWei-Yi HuA PCA and KDE Based Approach for Statistical CMOS Compact Model Parameter GenerationAuthorsYifan ZhouXuge FanAsen AsenovJie DingAccelerating IC Thermal Simulation Data Generation via Block Krylov and Operator ActionAuthorsHong WangWenkai YangJie WangHuanshuo DongZijie GengZhen HuangDepeng XieAddressing Sequential Constraints in Zoned Storage with Collective Log-Structured File SystemAuthorsChang-Gyu LeeYoungjae KimADEM: Accelerating Sparse Matrix Multiplication with Adaptive Dataflow and Efficient MergingAuthorsLuo shengbaiBo WangYihao ShiYuhan TangQingshan XueXueyi ZhangYunping ZhaoSheng maTiejun LiAdvanced Detection of Hardware Trojans in Post-Layout ICs: A GDSII-Focused MethodologyAuthorsYaroslav PopryhoInna Partin-VaisbandAn Efficient Wear-Leveling-Aware Parallel Allocator for Multiple Persistent Memory File SystemsAuthorsTing WuLinbo LongZhulin MaYulong ZhouWeichen LiuAn Experience Sharing: A Panoramic-Vision Lesion-Finding Low-Power Wireless Endoscopic System Design and ImplementationAuthorching-hwa chengAnalytical Optimization for Robust and Efficient Analog IC Design AutomationAuthorsAlec AdairArmin TajalliAnalytical Warpage-aware Multi-die Floorplanning for Advanced Package DesignsAuthorsShao-Yu LoMin-Hung ChenYao-Wen ChangBoolean Reasoning Guided UngroupingAuthorsEleonora TestaGiulia MeuliElena TeicaAlan VazVishal AralikattiAbhishek KumarBrian LockyearLuca AmaruCarbonEDA: Carbon-Aware Electronic Design Automation for Integrated CircuitsAuthorsDavid KongDanielle Grey-StewartMariam ElgamalGage HillsCD2A: Continuous Device-to-Device Authentication Exploiting Crystal Oscillator ImpuritiesAuthorsmuthupavithran selvamZeba KhanamAmit Kumar SinghZhan CuiMuttukrishnan RajarajanCIRCUITSYNTH-RL: LLM-Based Circuit Topology Synthesis with RL RefinementAuthorsPrashanth VijayaraghavanLuyao ShiEhsan DeganVandana MukherjeeXin ZhangConNAS4ML: Constraint-Aware Differentiable Neural Architecture Search for Efficient FPGA DeploymentAuthorsChi-Jui ChenBo-Cheng LaiCPCRFUZZ：Critical Path and Control Register Directed Fuzzing for Hardware VulnerabilityAuthorsLei PengAijiao CuiWei ZhangGang QuCrosstalk-Aware Mapping for Optical Neural NetworksAuthorsYuetong FangZiqing WangRenjing XuA Highly Energy-Efficient Binary BERT Model on Group Vector Systolic CIM AcceleratorAuthorsDingbang LiuZiyi GuanQilong ChenJiaqi YangKai LiMingqiang HuangChangwen ChenNgai WongHao YuDiReC: Enhancing VHDL Code Generation and Summarization with Divide-Retrieve-Conquer StrategyAuthorsPrashanth VijayaraghavanApoorva NitsureLuyao ShiCharles MackinTyler BaldwinDavid BeymerEhsan DeganVandana MukherjeedyGRASS: Dynamic Spectral Graph Sparsification via Localized Random Walks on GPUsAuthorsYihang YuanAli AghdaeiZhuo FengDyna-Optics: Architecting a Channel-Adaptive DNN Near-Sensor Optical Accelerator for Dynamic InferenceAuthorsDeniz NajafiWanhao YuMehrdad MorsaliPietro MercatiMohsen ImaniMahdi Nikdastli yangShaahin AngiziEfficient Edge AI Learning with Equilibrium Propagation: A Practical Solution For Gradient ComputationAuthorsMohamed WatfaAlberto Garcia-OrtizGilles SassatellieMamba: Efficient Acceleration of Mamba Models for Edge ComputingAuthorsJiyong KimJaeho LeeJiahao LinAlish KananiUmit OgrasJaehyun ParkEnhancing LLMs for HDL Code Optimization using Domain Knowledge InjectionAuthorsChe-Ming ChangPrashanth VijayaraghavanCharles MackinAshutosh JadhavHsinyu TsaiVandana MukherjeeEhsan DeganA Tensor-Train Decomposition Compressed LLMs on Group Vector Systolic AcceleratorAuthorsSixiao HuangTintin WangAng LiAo ShenKai LiKeyao JiangMingqiang HuangHao YuAn Innovative Memory Design with Internal ECC Functionality Based on In-Memory ComputingAuthorsBai NaLi GangXu YaohuaWang YiMing TianboXu YongjianLiu BiweiBlack-box Auto-Tuning for Customized SSD Firmware Parameters under ConstraintsAuthorsKibeen JungChangyong OhHyun-kyo OhByeonghui KimHankyu LeeSeongho RohYoungjae BaeDonghyub KangSangkwon MoonKangho RohJisoo KimSangyeun ChoJongyoul LeeCLEAR-HD: Computationally Light and Effective Unlearning for Hyperdimensional ComputingAuthorsFatemeh AsgarinejadTajana RosingBaris AksanliCompact Thermal Model-Based Analytical 3D Chip Placement with GPU AccelerationAuthorsZijie GengZhaojie TuJie WangYuxi QianSiyuan XuMingxuan YuanJianye HaoComputing-In-Memory Dataflow for Minimal Buffer TrafficAuthorsChoongseok SongDoo Seok JeongDAPO: Design Structure Aware Pass Ordering in High-Level Synthesis with Graph Contrastive and Reinforcement LearningAuthorsJinming GeLinfeng DuLikith AnapartyShangkun LiTingyuan LiangAfzal AhmadVivek ChaturvediSharad SinhaZhiyao XieJiang XuWei ZhangDead Gate EliminationAuthorsYanbin ChenHelmut SeidlChristian MendlDirected on-the-fly Validation of Hierarchical Cache Coherence ProtocolsAuthorsAbhinaba ChakrabortyAnsuman BanerjeeVinay B.Y. KumarArindam MallikEdge Continual Learning with Mixed-Signal Gaussian Mixture-based Bayesian Neural NetworksAuthorsSteven DavisZephan EncisoLikai PeiJianbo LiuBoyang ChengDanny ChenNingyuan CaoEfficient Runtime Management of Crossbars for Path-based In-Memory ComputingAuthorsSven ThijssenMuhammad Rashedul Haq RashedSumit JhaRickard EwetzEvoSolo: Evolutionary Sequence Optimization for Logic Synthesis with Cascaded PPOAuthorsJiaxing WangDan FengKang LiuFARM: Fast Acceleration of Random forests via in-Memory processingAuthorsAymen AhmedValeria BertaccoFAxC: Exploiting Feature Approximation for Privacy Preservation in Human Activity RecognitionAuthorsNishanth ChennagouniSandeep SunkavilliQiaoyan YuFast random walk through reduction of absorbing Markov chainAuthorsWonjae LeeDaijoon HyunYoungsoo ShinFuncFormer: Circuit Representation Learning via the Flow of Functional PropagationAuthorsZhihai WangYunjie JiJie WangMin LiJunhua HuangZhihao ShiMingxuan YuanJianye HaoGenesis: A Spiking Neuromorphic Accelerator With On-chip Continual LearningAuthorsVedant KariaAbdullah ZyarahDhireesha KudithipudiGTA: An Instruction-Driven Graph Tensor Accelerator for General GNNsAuthorsKai ZhongJin SiZhenhua ZhuQiushi LinMarc NeuJuergen BeckerHuazhong YangYu WangGuard Ring- and Diffusion-Sharing Embedded FinFET Array PlacementAuthorsShih-Yu ChenTzu-Hsiang WeiHao-Ju ChangHung-Ming ChenChien-Nan LiuHeterogeneous Approximate Multiplications: A New Frontier for Practical DNNsAuthorsSalar ShakibhamedanNima AmirafsharAxel JantschNima TaheriNejadHLSRanker: Design Space Exploration in High-Level Synthesis Using Preference Bayesian OptimizationAuthorsRenjing HouDonghao GuoZhe LinPeng XuJiawei LiuJianwang ZhaiKang ZhaoInherent Vulnerability of Atomic Patterns due to Distinguishability of Field Multiplication and Squaring OperationsAuthorsAlkistis SigourouZoya DykaPeter LangendoerferIevgen KabinLEDRO: LLM-Enhanced Design Space Reduction and Optimization for Analog CircuitsAuthorsDimple KocharHanrui WangAnantha ChandrakasanXin ZhangLLM-Driven TPU Design: Crafting Custom Tensor Processing Accelerators with APTPU-GenAuthorsDeepak VungaralaMohammed E. ElbtitySumiya SyedSakila AlamKartik PanditArnob GhoshRamtin ZandShaahin AngiziLUT-MM: An Efficient Lookup Table-Based Approach for Modular MultiplicationAuthorsZhaoyuan LiKun YangKui RenMachine Learning Driven Early Clustering for Multi-bit Flip-Flop AllocationAuthorsJooyeon JeongTaewhan KimMetaGuard: Transforming Run-Time Hardware Trojan Detection using Meta Reinforcement LearningAuthorsZhangying HeThomas NguyenHossein SayadiModeling PFAS in Semiconductor Manufacturing to Quantify Trade-offs in Energy Efficiency and Environmental Impact of Computing SystemsAuthorsMariam ElgamalAbdulrahman MahmoudGu-Yeon WeiDavid BrooksGage HillsNavigating the Trilemma: Security, Power, and Performance Trade-offs in Bluetooth Low EnergyAuthorsNing MiaoChongzhou FangRuijie FangRuoyu ZhangSetareh RafatiradHossein SayadiHouman HomayounNon-Negative AdderNet (NNAN): Can We Make DNNs More Secure and Efficient Without Multiplication?AuthorsYunxiang ZhangSabbir AhmedAbeer AlmalkyAdnan Siraj RakinWenfeng ZhaoOne Gray Code Fits All: Optimizing Access Time with Bi-Directional Programming for QLC SSDsAuthorsTianyu WangShaoqi LiYongbiao ZhuFuwen ChenChenlin MaZhaoyan ShenRui MaoYi WangOrdering-Centric: A Scalable and Exact Method for Scheduling with Resource ConstraintsAuthorsMeng GaoJiacheng ZhaoHuimin CuiXiaobing FengOptimal Front vs Back-side Signal Allocation for PPA Improvements in Advanced CMOS Featuring Back-side Metal InterconnectsAuthorsNishant GuptaSirish OrugantiSai Subrahmanya Teja NibhanupudiAnup Ashok KedilayaXiuhao ZhangJaydeep KulkarniDES5: Emerging Device and Interconnect TechnologiesOut of The Box Techniques for Data Path VerificationAuthorsAtharva KakdeKetki GosaviPradeep BagavathiappanAnshul SinghalSorna InianQuantum Secure Hash Oracle (QSHO): Strengthening Post-Quantum Cryptography with Kyber-AES, Grover's Simulations, and Hybrid Attack ResistanceAuthorsMohamed YaqubAdarsh AnandhakumarSudikshan SenthilkumaranNavin BalajiGayathri ManiPushpalatha MOpt-MC: A Graph-based Placement and Routing Algorithm for Optimizing Macro Cell DesignAuthorsByeongKeun KangYoonJung KimJungSeok HwangDooYoung LeeMooKyu BaeMinKwon OnHyunSeo KangJungSeok OhWanDong KimHyuckJoon KwonJiHo ChoKi-Whan SongSungHoi HurPacemaker: Energy-Efficient Speculative Scheduling Window Resizing without Performance ImpactAuthorsJeonghoon ChoiIpoom JeongWon Woo RoPaGO: Pareto-Assisted Goal Optimization for Analog Circuit SizingAuthorsYoungchan JoJaemyung LimPanther: A PIM-based Blockchain Database System Supporting Efficient Verifiable QueriesAuthorsYifan HuaShengan ZhengWeihan KongYuheng WenLinpeng HuangParLS: A Logic Synthesis Framework based on Circuit Partitioning and Reinforcement LearningAuthorsXingyu QinGuande DongJianwang ZhaiKang ZhaoPipeSpec: Breaking Stage Dependencies in Hierarchical LLM DecodingAuthorsBradley McDanelSai Qian ZhangYunhai HuZining LiuPI-Whisper: Designing an Adaptive and Incremental Automatic Speech Recognition System for Edge DevicesAuthorsAmir NassereldineDancheng LiuChenhui XuRuiyang QinYiyu ShiJinjun XiongPlace-and-Route for Photonic Integrated Circuits using Industry-Standard EDA ToolsAuthorsGeorgios KyriazidisJohn DavisJui-Hung ChangChih-Lung LinGage HillsPMICO: Power Management Integrated Circuits Optimization Framework Using Multi-Agent Reinforcement LearningAuthorsHan WuHaoqiang DengYan LuBo YuanJunmin JiangPPA-driven Placement via Adaptive Cluster Constraints OptimizationAuthorsZiyan LiuSiyuan XuJie WangZijie GengYeqiu ChenMingxuan YuanJianye HAOFeng WuProcess Design Kits for Co-Designing Broadband Integrated Photonics and Silicon CMOS in Electronic-Photonic VLSI CircuitsAuthorsGeorgios KyriazidisJohn DavisJui-Hung ChangHana WarnerNorman LippokChih-Lung LinBenjamin VakocMarko LoncarGage HillsPromptV: Leveraging LLM-powered Multi-Agent Prompting for High-quality Verilog GenerationAuthorsZhendong MiRenming ZhengHaowen ZhongYue SunShaoyi HuangRainy Noise Cancellation Technique for LiDAR System Using Convolution Neural NetworkAuthorching-hwa chengRethinking the Distribution of Outliers in Large Language Models: An In-depth StudyAuthorsRahul RamanKhushi SharmaSai Qian ZhangRethinking Translation Robustness for Reliable Convolutional Segmentation ArchitectureAuthorZherui ZhangROPE-MLA: Row-Access Optimized Processing Element Machine Learning AcceleratorAuthorsPrasanth Prabu RavichandiranPaul FranzonW. Rhett DavisTianfu WuFranc BrglezRTLExplain: A Structured Approach to RTL Code Summarization and Question Answering for Medium-to-Large Designs Using LLMsAuthorsTing-Hsun ChiCharles MackinLuyao ShiPrashanth VijayaraghavanHsinyu TsaiEhsan DeganScaleX: A Scalable and Flexible Architecture for Efficient GNN InferenceAuthorsTingting XiangMiao YuTrevor E. CarlsonSelf-Supervised Learning based Etching Process Modeling: Bridging Simulation and Experimental DataAuthorsZhenjie YaoZiyi HuZhiqiang LiDashan ShangRui ChenLing LiSLTarch: Towards Scalable Point-Based Neural Rendering by Taming Workload Imbalance and Memory IrregularityAuthorsXingyang LiJie JiangYu FengYiming GanJieru ZhaoZihan LiuJingwen LengMinyi GuoSystemVerilog Assertion Syntax Correction with Knowledge Distillation: Toward LLM-Guided Automated Hardware VerificationAuthorsDipayan SahaChandra BhagavatulaRyan EigerKartik HedgeHamid ShojaeiFarimah FarahmandiSynthesis of a memristor-transistor single-phase cell library and its use to synthesize logic circuitsAuthorsBaishakhi Rani BiswasSandeep GuptaDES5: Emerging Device and Interconnect TechnologiesTowards Accurate, Real-Time, and Energy-Efficient Attention MonitoringAuthorsAnice JahanjooVimala BauerSoheil KhooyoozMostafa HaghiNima TaheriNejadTowards Multi-Objective Routing: A Novel Coreset-based Transfer Learning FrameworkAuthorsXianglu WangHu DingTransistor Placement Routability Prediction for Standard Cell DesignAuthorsVitor Hugo FuerstenauFelipe BortolonMarcos BackesEduardo BarbianRicardo ReisTrustChain AI: A Privacy-Preserving Decentralized Architecture for Large Language Model AggregationAuthorsArpita SarkerAlexander JesserValidating the Design of CPS: Interfacing Simulations of Multi-Physics Components and Software with Contract-Based MonitoringAuthorsFriederike BrunsFrancesco TosoniSven MehlhopAndreas RauhSara VincoJörg WalterFrank OppenheimerFranco FummiEnergy-Efficient, Real-Time Robotic Path Planning through FPGA AccelerationAuthorsTanmay DesaiBrian PlancherRuth Iris BaharA Novel Standard Cell Structure and Physical Design Methodology to Enhance RoutabilityAuthorsSeongjun LeeChangho HanThe Art of Beating the Odds with Predictor-Guided Random Design Space ExplorationAuthorsFelix ArnoldMaxence BouvierRyuan AmaudruzRenzo AndriLukas CavigelliPOG: Parameter Optimization using Graph Neural Networks on Reinforcement LearningAuthorsSumin OhHyunJin KimSelf-Motivated Agents for Analog Circuit Optimization via Intrinsic RewardAuthorsSumin OhHyunJin KimQuantum Properties Trojans (QuPTs) for Attacking QNNsAuthorsSounak BhowmikHimanshu ThapliyalReliability-aware DTCO with Physics-Constrained Machine Learning Framework for MOSFETs Trap ExtractionAuthorsJinghan XuZheng ZhouXiaoyan Liu
