Session Full Program · Contributors · Organizations · Search Program · Flagged · Happening NowMore…Search ProgramFlaggedHappening NowEngineering Poster, Networking: Monday Engineering Tracks Poster ReceptionEvent TypeEngineering Poster, NetworkingTimeMonday, June 235:00pm - 6:00pm PDTLocationEngineering Posters, Level 2 Exhibit HallSimilar SessionsGrid Resilience - Powering Solutions Design and Delivery for the Performance PromisesNovel Eddies in the Implementation FlowVerification Innovation: Shaping the Future of Design ValidationPresentationsOptimizing Network Storage for AI-Powered EDA DeploymentsAuthorPrathna SekarMethod of Constraint Transformation in Static Timing Analysis for Dual Edge TimingAuthorsJack DiLulloEric ForemanManish VermaXin ZhaoAdvanced Yield Prediction for SRAM Bitcells with Rare Defect Modeling Leveraging AI-Powered MethodologyAuthorsMohamed AtouaSandeep PuriGenerative AI for improving the productivity in Analog & Mixed Signal design flowsAuthorsNupur BhongePrathna SekarReusable and Efficient Scoreboard Implementation for bug hunting and testbench productivityAuthorsSougata BhattacharjeeGulshan SharmaGuru ChapiAutomated IR-ECO Flow : Reducing PDN Violations upto 40-50% and Saving Weeks of Engineering EffortAuthorsMohit JainRoshan RoyLen HsuA Novel Approach For Logic Equivalence Check After Pipeline Retiming in ECOAuthorsNaveen BishnoiSardar BhukyaMohit RawatSneha BiswasSatish SethuramanBassilios PetrakisNilabh SrivastavaEnhancing Timing Closure in High-Frequency Designs through Precise Latency Control and Timing-Aware Sink AssignmentAuthorsNaveen BishnoiRoopa TigadiKishan RameshNilabh SrivastavaGowry SankarDesign Floorplan-Driven Localization of SMS Processors for Optimized Memory PerformanceAuthorsA S Ramkumar ReddyLakshmi Sarvaani PallapuR Santhosh KumarAnil kumar EdeA Novel Test Point Insertion Methodology for Enhanced Test Efficiency and Improved Design QualityAuthorsPervez GargPiyushkumar ChaniyaraInterconnection Testkeys Enable BEOL-Process Monitoring and RC Accuracy ImprovementAuthorsKun ZhouJian WangZhikun LiuXiaochuan WangGuohua ZhouKeqing OuyangCongestion Free, Power Domain Aware Signal MultiplexingAuthorsDinesh JoshiNidhi SinhaSpreadsheet Automata: A Systematic Approach to Executing Spreadsheet State Machines in C++ Performance ModelsAuthorsZachary AnkenmanBiju Puthur SimonRamesh Krishna JayaramanReal-time Process Margin-based Layout OptimizationAuthorsCollin TranterNavneet JainRomain FeuilletteDavid PritchardHeather LazarNolan PavekStephen BurgessBenoit RamadoutAdvanced APL Modeling Method for Complex I/O Buffer Designs for accurate SoC IR Drop AnalysisAuthorsjean francoisAnil DwivediAtul BhargavaAnkur BalOptimizing Power Integrity with Smart PDN FrameworkAuthorsGaurav JainRajender NuneVinay Kumar B USrihari DarapuUsing Big Data and ML techniques to triage timing violationsAuthorLukas PetterssonHierarchical EM-IR Signoff Methodology for large SoCs integrated in 2.5DIC StructuresAuthorsSumanth SuraneniNikhil JayakumarMaryam MoradpourAnsh DudejaEnsuring DRAM Compliance: Novel Verification Techniques for Refresh and Refresh Management in Modern Dram ArchitectureAuthorsShyam SharmaGruheshkumar PatelDharini SubashchandranAutomated AI-ML based flow for Validated Constraint Generation for CDC/RDCAuthorAbdul MoyeenFast-tracking PCIe Verification in an SoC by automating the testbench using triple Check test-suiteAuthorsSubramanian RSekhar DangudubiyyamNaga Swetha MaddulapalliHBM Timing Methodology with Liberty LVFAuthorsEric HsuYing LuoAN-JUI SHEYEnhanced LVS Techniques for Fast Convergence and Optimized Design CyclesAuthorsVandana NarulaErtugrul DemircanGAZAL SINGLARevolutionising SOC Verification through System Verilog EEnet-Enhanced Behavioural Model for Precision in Analog IP CharacterisationAuthorsAadhar SharmaSooraj SekharLakshmanan BalasubramanianBhavya ShahAvinash ChaudharyStefan Dannenberger"Optimizing Timing Convergence in High-Speed PCIe Systems: An EDA Methodological Approach"AuthorsKeshavkumar DurgakeriAnilkumar EdeA Subbaramkumar ReddySaidesh PasupuletiMachine Learning Based Layout Optimization of Electromagnetic Structures for High-Speed IO DesignAuthorGarth SundbergSolving Configuration Challenge with SVRAND Verification FlowAuthorsKrunal KapadiyaKaushal ValaJoseph BauerShyam SharmaAI/ML Driven Optimization for Efficient ATPG in Large Scale DesignsAuthorsPervez GargPiyushkumar ChaniyaraSatish SajjanarMethod & Apparatus to Migrate Design Repositories into CloudAuthorsNupur BhongePrathna Sekar3D-IC Heterogeneous System Implementation using Virtuoso Studio and Integrity System PlannerAuthorsGourav UppalAmit KumarHitesh MarwahChayan MajumderDan BaldwinExpediting custom core SOC verification and coverage driven firmware sign-off using ESWD & Verisium DebugAuthorsAyushi BapnaArif MohammedYogeshwaran ShanmugamAshwini PadoorStreamlined RTL Clock Management: A Python Framework for Clock Tracing, Clock Spec Verification and STA Constraint GenerationAuthorsTejas SalunkheFaeq HussainUsing AI to validate standard cell Liberty IP riddled with sparse and disparate dataAuthorsRay ValenciaAjay KumarAravind Radhakrishnan NairA Safety Centric approach to Functional Verification of Dual Core Lock-Step DesignsAuthorsMohammad RashidSuharini CRatan DeepHarsh SetiaPPA Friendly Custom Repeater Tree Insertion for High-Speed DesignsAuthorssachin mirajkarSarala GummaCircuit Design and Optimization Methodology ensuring Area optimized, Robust and Reliable I/O Interface for Wide Range of Application useAuthorsANUJ GUPTASuprbha KumariAnil DwivediAutomated "Spec to Sign-Off" of CSR and Integration Verification at SOCAuthorsSai Nikhil KandukuriSwathi NagarajasettySunil KashideGarima SrivastavaVijaya GuptaGopikrishna KommidiIntegrating Self-Heat Analysis in Multiphysics Simulation for Advanced Semiconductor Chip DesignAuthorsStuti SinghPritesh JohariArian FanaianAn Efficient Methodology of Analyzing Rush Current in Power Gated DesignAuthorsAbhinav GaurAkhilesh MishraAnkur ChavhanMethodology to Generate Synthesis Signoff Quality Optimized Registers at RTL and Application of Generated Optimized Registers into RTL and Implementation Design Flows to Improve ProductivityAuthorssuresh barlaBHAVANA MALLIKARJUNAIAHHimanshu KathuriaJaskaran AjimalHigh-Capacity, High-Performance Chip-Level ESD Analysis for Reliable Semiconductor DesignsAuthorsVinoth MurugesanKumar AvalaLeveraging Machine Learning to Automate Waiver Generation for Static Lint ViolationsAuthorsMohan MangalHimanshu KathuriaJaskaran AjimalA constructive approach to Left-shift preliminary identification of critical silicon breaking anomaliesAuthorsAyushi BapnaArif MohammedIR-Aware Timing Analysis using Accurate DvD-PWL Flow for Advanced Technology NodesAuthorsRajnish GARGAnil YadavActive Device Testkeys Enable FEOL-Process Monitoring and Performance ImprovementAuthorsZhikun LiuXiaochuan WangKun ZhouJian WangGuohua ZhouKeqing OuyangComprehensive solution for Optimizing and Accelerating Gate level simulation for complex SOCsAuthorspradeep sahooSunil KashideGarima SrivastavaNarasimha ChinniShekhar SharmaPrem SinhaAutomated IR convergence with PrimeClosure IR-ECOAuthorsShreya Mysore PandurangaHailang WangJimmy WuPiyush JainRossana LiuSrinivasulu MAccelerating System Validation using Emulation and FPGA Prototyping PlatformsAuthorsPonnambalam LakshmananAjeet MallChip package level thermal integrity analysis of high-power data center chips for hot spot detectionAuthorsSumanth SuraneniNikhil JayakumarSujyesh Aanandh ManjunthanA new methodology to generate a multitude of SoC configurations quicklyAuthorsFernand Da FonsecaChouki AktoufValentin BoyerMael RabeDesign Optimization of ASIC Designs via AI-driven RTL-to-GDS Optimization with FloorplanningAuthorsJennifer KazdaWachirawit PonghiranAnindita GangwarBen BeaumontDerren Dunntiming-aware smart PG fillAuthorsRahul pandeyAnil yadavAnkur ChavhanBiswarup PalDavinder AGGARWAL
