Session Full Program · Contributors · Organizations · Search Program · Flagged · Happening NowMore…Search ProgramFlaggedHappening NowEngineering Poster: Tuesday Engineering Tracks Poster ReceptionEvent TypeEngineering PosterTimeTuesday, June 245:00pm - 6:00pm PDTLocationEngineering Posters, Level 2 Exhibit HallSimilar SessionsVerification Innovation: Shaping the Future of Design ValidationGrid Resilience - Powering Solutions Design and Delivery for the Performance PromisesNovel Eddies in the Implementation FlowPresentationsScalable Debugging for Data Centers: Ensuring Reliability from Design to OperationsAuthorsSuresh DuthiraruRolf KuehnisSandesh PutturayaMatthias ZensGuided Physical Power Optimization of AI SiliconAuthorAditya Chandrasekar RamachandranAI-Based Trimming and Optimization for Voltage Regulators: Proven Accuracy with Wafer DataAuthorsDoyoung KimTei ChoEunsuk ParkSungyoun LeeMohamed AtouaWonbeom ChoiBonggil KangA Comprehensive Electromagnetic Analysis Flow for Die and Package Joint Model Simulation of RF Chips DesignAuthorsChaofan ZengJie HuXiaoming SiYongsheng GuoAutomated Topology based Pin Access Checker for Correct by Construction Standard Cells DesignAuthorsSHARMISTHA SINHAAnuradha RayAnand MishraFrederic AvellanedaAkshita BansalHitesh MarwahArvind KumarNeha AgrawalVishesh KumarAtul BhargavaAnkur BalAnil DwivediPower-aware DFT-driven High Confidence EMIR Signoff for Low Power Automotive SoCsAuthorsShining DongGlen GeRong WangShuoyue CuiChang ZhaoPhysical Design Independent-IR solver for early first cut SoC PG analysisAuthorsPrateek PendyalaJingwei ZhangT Govindaswamy Rahul SaiSoft Error Simulation Tools, From 45nm to 3nmAuthorsJC BouziguesMaximilien GlorieuxIssam NofalPhysical Aware RAM Sequential ATPG for IR PreventionAuthorsChen Yuan KaoJerry ChenAccelerated ESD Sign-Off Solution: An Efficient and Scalable ApproachAuthorsSmaritha KasukurthiMathew KaipanatuSainath Reddy GummanaSai Prabhakar AtluriInnovative RDL PEX flow with Calibre, enhances design reliability and performanceAuthorsSrilata RamanHaritez NarisettyDavid PermanaYousry ElMaghrabySalma YoussefPattern-based Abstraction for Mixed Transistor-Level Static Timing AnalysisAuthorsXin ZhaoRobert AllenKerim KalafalaEffective Ways of Analyzing and Optimizing Voltage Variation Challenges for 3DIC ChipsAuthorsmingyang liuRunjian WangRan ZhangHengzhi Huminglu xuYue HengLong KongShuoyue CuiXiaomei YouNovel Shift-Left Methodology for System Power Integrity Analysis with Early Chip Power ModelAuthorsLyubomir KerachevOlivier BayetRavi ThiruveedhulaFormal meets Simulation: Accelerate Verification closure using Multiplatform technologiesAuthorsAnunay BajajAmrita PatilKirti Srivastava1.1% Die area reduction in Consumer and Industrial MCU-Production SoC meeting Analog Routing and performance TargetsAuthorsAbhishek NigamAshutosh ChaubeyYusuke TanabeJuntaro AkashiSeiichi OshimaToru SugaharaJayapriya ArjunanUSB4 MAC Verification: Overcoming Serial Interface and Simulation Time ChallengesAuthorsNehal PatelNirav ToliyaA Robust and Efficient Verification Suite for AMS IP HDL Models for Streamlined SoC IntegrationAuthorsRahul KumarAnil DwivediAnkur BalAtul BhargavaDetection of Functional and Current Related Bugs in SoC through Full Chip SPICE Simulations (FCS)AuthorsManmohan RanaNishant KaundalRakesh ShenoyAn Efficient Hierarchical Chip-Top Level EMIR Signoff Methodology for Large Automotive SOCs.AuthorsAkhilesh MishraAbhinav GaurRamesh SharmaShreyashi JaiswalRecipe Explorer: Crafting the Missing PD Flow LayerAuthorAditya Chandrasekar RamachandranTiming Visualizer AI Assistant: A Novel Machine Learning Application for Efficient Timing TriageAuthorsSantanu DasNidhi GuptaKerim KalafalaCharles GatesChakradhar ThallapakaHaritha MudimelaPrabhat MauryaHemlata GuptaAryan GargIndramani YadavSachin GuptaGireesh kumar K MENZO: Comprehensive DFT Methodology for MCU class of devicesAuthorsArshdeep SinghJahnavi PragadaVishal DiwanYogeshwaran ShanmugamAdvanced State Space Tunneling: Debug Your Formal Complexity Using Waveforms!AuthorsErik SeligmanLars LundgrenMariane GoncalvesGustavo JunquieraTulio LeaoGabriela BahiaHakan HjortCraig DeatonVarun RameshVarun RameshMaximizing IR sign-off coverage using Sigma-AV and its benefit on PPAAuthorsSandeep GajbhareMathew KaipanatuAutomated QA for Standard Cell Libraries used in RAIN RFID ChipsAuthorsKeven DunnCooper RobertsonLee BurnsJanus – twin-faced debugging - Anecdotes from formal, security & timing exception verificationAuthorsSrinivasan VenkataramananAjeetha Kumari VenkatesanHemamalini SundaramPortfolio Re-characterization using AIAuthorsRay ValenciaAjay KumarReshma KrishnakumarSwanand KulkarniAbhishek SharmaAI-ML meets SPICE to achieve 6-sigma Accuracy: A Revolution in Statistical AnalysisAuthorsaditya vasisthRajesh NarwalPravesh SainiPrayes JainAccurate Memory IR Sign-Off at Lower Tech nodesAuthorsSmaritha KasukurthiMathew Kaipanatuakshay guptaAccelerating Semiconductor Test Data Analysis through CPU-GPU Hybrid Computing: A Resource Optimization FrameworkAuthorsanghyeok parkIC Folding for Enhanced Performance in Homogeneous RF-AMS SystemsAuthorsParv MalhotraNeha AgrawalHitesh MarwahMike LinArnold GinettiPraveen PillaiJignesh PatelAditya RameshaDesign Quality Improvement Through AutomationAuthorsSagar JogurMangesh DhantoleAudit Flow: A fast quality checker tool for early design convergenceAuthorsManjunath NayakSubhash UppalaAnoop SinghAyan DattaSimulation-Aware Gate Resistance Modeling before Post-Layout SimulationAuthorsHsiu-Chuang ChangHsiang-Ho ChangKe-Ying SuChip reliability with antenna discharge path considerationAuthorsHeng Lan LauJohn FergusonLing LeiApproach For Quality DV Using C2RTL For Algorithmic Designs Authors: Neema Agarwal, Himanshu Chauhan, Harsh Setia, Atharva Mahesh Kakde, Ketki GosaviAuthorsNeema AgarwalHimanshu ChauhanHarsh SetiaAtharva KakdeKetki GosaviCTS with Machine Learning NDRAuthorSungsu ByunEfficient Translation of OpenAccess Design Data to the OASIS® FormatAuthorsRobert AllenMitch DeHondRon RoseMargaret AllenMatt GuzowskiNayo Ogilvie18% Die area reduction in UWB Automotive Production SoC meeting performanceAuthorsAbhishek NigamVinod SinghNilotpal ArjunSwati SinghSateesh PotnuruS DeepikaBhanu PrakashNaoki UedaMasafumi IeiriYusuke OkazakiAutomated – BUS Routing Solution for Efficient DRC clean TestChip DesignAuthorsManvi DhawanAtul BhargavaRajeev SinghAkshita BansalFabien CampanaLaurent Saint-MarcelAnil DwivediAnkur BalPeak Power Optimization in RTL2GDS flow using guidance from RTL Power Optimization toolsAuthorsSanchita GuptaManish KumarVijay TayalAmit DeyOuidiane CHAFIKKamal Ait-cherguiYoussef SaroukhSoufian BouaziziFaheem Ahmed QaziA Novel Solution for Parasitic resistance analysis: Calibre PERC-Driven Optimization for PEX Quality AssuranceAuthorsJaeyoung Sotaeyoon LeeMinho JungKyunghan KangSeunghyun LeeSunsoo ByunValidation journey of SOC High Speed Interfaces: From sim to real deviceAuthorsRahul SomanJyothish BalakrishnanFront-End Design
