Session Full Program · Contributors · Organizations · Search Program · Flagged · Happening NowMore…Search ProgramFlaggedHappening NowEngineering Poster, Networking: Wednesday Engineering Tracks Poster ReceptionEvent TypeEngineering Poster, NetworkingTimeWednesday, June 2512:15pm - 1:15pm PDTLocationEngineering Posters, Level 2 Exhibit HallSimilar SessionsNovel Eddies in the Implementation FlowVerification Innovation: Shaping the Future of Design ValidationGrid Resilience - Powering Solutions Design and Delivery for the Performance PromisesPresentationsBoosting Low Power Verification Methodology: Introducing Power-Aware Formal Property Verification into the FlowAuthorsGianluca RiganoDavid VincenzoniPatrick BlestelEasy AI for STA teamsAuthorTim HelveyEnhancing Design Quality through a High-Level Synthesis Flow in Neural Network-Based Keyword Spotting SystemsAuthorsGianluca RiganoLuca Francesco PerroniMario BlangifortiSavino BellopedePaolo MazzettiEnrico PapaMichele PalmaGiuseppa Maria PinoAutomated modelling and assertion generator for verifying any generic complex IO ControllersAuthorsAyush JodhKumar SinghParthasarathy RameshHarish MaruthiyodhanEarly Clock Network Jitter EstimationAuthorsTusharkant Mishrapradeep kothariAyan DattaClock H-tree exploration in BSPDNAuthorsJongbeom KimDayeon ChoWook KimKi-ok KimHyung-Ock KimSTA Dashboard: Leveraging Data Analytics for Effective Static Timing AnalysisAuthorsManjunath NayakSubhash UppalaAnoop SinghAyan DattaAn Efficient Methodology for Multi-PVT EMIR Analysis of Large SOCsAuthorsRamesh AgarwalAnusha VemuriRajvi ShahEmmanuel ChaoSantosh SantoshPratik ShahAnush SharmaShreya SashiNaveen BBuilding a Parallel Simulation Kernel for Faster & Better Virtual PlatformsAuthorJakob EngblomAutomation of Shmoo Engine based Pre-Si BDI TestingAuthorsMohit ShrivastavaPrachi MishraRakesh BansalKrishan PrajapatActivity-Based Power Density OptimizationAuthorsSravanthi GajjalaKaranvir SinghRakesh KumarVinesh JayaramanAshish KumarSatish SethuramanNilabh SrivastavaReducing Top Level Verification Cycle of High Frequency PLLs with Enhanced Fast-SPICE TechnologyAuthorsAnkit GuptaAtul BhargavaNitin JainPrayes JainAnkur BalAnil DwivediAutomated generation of ISO 21434 Verification Work ProductsAuthorsMohit ShrivastavaPrachi MishraA Solution for intermittently and Fastly Power On RepairAuthorsMinqiang PengZhuo WangFeilong PanTianjiao WangJunhua QinHu HaiLei ChenKeqing OuyangGuohua ZhouJian YuFengfeng TangIP-Report: Methodology to Identify Simple Yet Effective Module Based Power Saving TechniquesAuthorsSUSEELA BUDISanjeeth Reddy AyanalaPraveen NarendranathANBAR hichamAnmol GargMohammed FahadManish KumarVishal KashyapVishnu KanwarDivya BarejaA DFT parallel test technologyAuthorsQi ChengZhijun LongMinqiang PengTianjiao WangPengfei XiChenyang ZhangKeqing OuyangGuohua ZhouXianjun ZengOn-Die Power Noise impact on High-Speed Signal Integrity (SI) of Photonics computing chip base on 3D Heterogeneous IntegrationAuthorsxinyuan miaoyongjie zhugrant zhangwayne wuHenry HeJohnny FengTao WangXiaodong WangAccelerating Chip Design with AI-Powered Additive Learning for Deep Sub-Micron TechnologiesAuthorsMohamed AtouaAmit BansalRaju RaasaAjaj AnsariVishal KulshresthaAgentic AI Approach to Optimize Front-End EDA Tools FlowAuthorsNitin PundirMaya SafieddineArvind HaranRich CarboneFrank WallingfordAli El-ZeinViresh ParuthiDan CoopsHeatSync: Machine Learning-Driven Floorplanning for Optimized Power Integrity and Thermal Integrity in Advanced PackagesAuthorsJisoo HwangKiHun OkMyunghoon LeeSubodh DeodharKi Wook JungSoYoung KimSingle Corner Mixed Voltage Functional Noise AnalysisAuthorsSteven KurtzMichael SitkoRahul RaoSanjay UpretiAjith ChandrasekaranHierarchical Early Latchup Checking FlowAuthorsYamini RavishankarSanghmitra JhaGreg FordUnlocking the power of AI-based verification apps for an innovative and efficient digital verification flowAuthorDavide SanalitroInnovative and Cost-Effective Approach to ESD Reliability Verification in the CloudAuthorsGAZAL SINGLAErtugrul DemircanDesign for Time Interleaving of Data using Sub-sampling ClocksAuthorAradhana KumariThermal Aware Design Optimizations and Signoff Using RHSC-ElectrothermalAuthorsRajvi ShahEmmanuel ChaoSantosh SantoshChris OrtizSabya MallickVaibhav RajputESD EDA Verification Flow Applied to Smart Power IC'sAuthorsChiara BielliStefano AngeliSigmaAV: High Global and Local Noise Coverage Solution for Power Integrity SignoffAuthorsAnusha VemuriVishal MalikEmmanuel ChaoSantosh SantoshChidambaram RakkappanEd DeetersEnhancements in Cell-Aware UDFM Models to Optimize the Development Flow of Custom Macros/IP and Standard Cell LibrariesAuthorsRavi J NPramod GayakwadAndreas GlowatzPre-Validation Tool: Minimizing Errors, Maximizing EfficiencyAuthorsSamvedna JhaShruthi RavindraUtkarsh ChitranshContemporary PPAS Optimization Strategies in Physical Implementation of Digital SoCs – A Case StudyAuthorsSukhmani VirkUTKARSHA SUMANBen ThomasMegha MenduMurtaza TankiwalaKavithaa rajagopalanAccelerating IR Simulation Workflows with Automated Setup and Results Data Visualization Tools for Digital Designs using Voltus PlatformAuthorsNinad KhireYash ZavarKavithaa RajagopalanKeerthi NoriMurtaza TankiwalaRishabh SinghSubhadeep GhoshA X-mask Chip Fast Binning TechnologyAuthorsJiawei WangMinqiang PengLei ChenKeqing OuyangGuohua ZhouFrom Block, Chip to System - A Comprehensive flow for large FPGA Dynamic Power Integrity Sign-offAuthorsDengji DongChenxu GuoYiting LinYahui LiA New Virtual IP Modeling Methodology for Re-usability in Heterogeneous Virtual PlatformsAuthorsYoonjoong OhDongYoung LeeJinyoung HwangHaeun KimSeungik HaJinbeom KimJongsung ParkKyungsu KangSilwan JangExploring the Latent Space in a Variational Auto Encoder when Addressing Local Layout EffectsAuthorsRafael Toche PizanoRichard WachnikMichael MonkowskiImproving Digital Design performance and area using DSO.aiAuthorsMichele BattistaMario BlangifortiLuca Francesco PerroniLuca PulvirentiMassimo BertolettiAccelerating analog connectivity verification with Jasper: comparing formal methods to mixed simulationAuthorsDavide SanalitroEdoardo BolleaSign-off Challenges and Solutions in Power Integrity and Reliability Analysis of 2.5DIC Silicon InterposerAuthorsJiajun ZhaoGuifang ChenXiaodong WangYiting LinYuming SunPengyue YinDesign-for-Verification architecture to shift-left TTM and align test codebase in multi-chiplet SoCsAuthorsDavid AkselrodAlex BranoverRob PeltAnanth PallapothuNicola NicoliciConfidentiality Assurance: A Key Component of Hardware SecurityAuthorsVarun SharmaVikas SachdevaVinod ViswanathAutonomous Physical Design: Accelerating ASIC Design using Machine LearningAuthorsSarah AhmadJason ChowAyan DattaAn advanced multi-vector optimization methodology to enhance power performance in scaled-down technology nodes.AuthorsLakshmidas KGowry ShanmugamSravanthi GajjalaMitigating Routing Congestion in Automotive SoCs with ML based Power Grid OptimizationAuthorsGovind PalAmit JangraHarshul BansalMachine Learning accelerated distributed computing Place and Route framework for High Performance CPU designsAuthorsLoknath MoogiGowry ShanmugamSivaraman PRiya RajMohit GuptaSilicon Lifecycle Management in Automotive DesignAuthorsRajnish GARGAmerjeet KumarHarshil UPADHYAYAnil YadavHSTAF: Hierarchical Static Timing Analysis FlowAuthorsPardhu PavanAyan DattaHimanshu BansalVikash TReducing High di/dt Simultaneous Switching Noise in Advanced Multiprocessor SoCsAuthorsGovind PalAnil YadavAmit JangraHarshul BansalI/O Power Grid Analysis MethodologyAuthorDaniel KimNovel Methodology to Address ESD Verification Complexity of 2.5D/3D-IC DesignsAuthorHirotaka YamazakiCDC-RDC Inter-operable collateral StandardizationAuthorsAnupam BakshiBill GascoyneDon MillsMethod of Static Timing Analysis for Dual Edge Triggered Pulsed LatchesAuthorsKerim KalafalaHemlata GuptaManish Verma
