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DTSTAMP:20260402T024534Z
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DTSTART;TZID=America/Los_Angeles:20250623T144500
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UID:dac_DAC 2025_sess104_RESEARCH1166@linklings.com
SUMMARY:ChipAlign: Instruction Alignment in Large Language Models for Chip
  Design via Geodesic Interpolation
DESCRIPTION:Chenhui Deng, Yunsheng Bai, and Haoxing Ren (Nvidia)\n\nRecent
  advancements in large language models (LLMs) have expanded their applicat
 ion across various domains, including chip design, where domain-adapted ch
 ip models like ChipNeMo have emerged. However, these models often struggle
  with instruction alignment, a crucial capability for LLMs that involves f
 ollowing explicit human directives. This limitation impedes the practical 
 application of chip LLMs, including serving as assistant chatbots for hard
 ware design engineers. In this work, we introduce ChipAlign, a novel appro
 ach that utilizes a training-free model merging strategy, combining the st
 rengths of a general instruction-aligned LLM with a chip-specific LLM. By 
 considering the underlying manifold in the weight space, ChipAlign employs
  geodesic interpolation to effectively fuse the weights of input LLMs, pro
 ducing a merged model that inherits strong instruction alignment and chip 
 expertise from the respective instruction and chip LLMs. Our results demon
 strate that ChipAlign significantly enhances instruction-following capabil
 ities of existing chip LLMs, achieving up to a 26.6% improvement on the IF
 Eval benchmark, while maintaining comparable expertise in the chip domain.
  This improvement in instruction alignment also translates to notable gain
 s in instruction-involved QA tasks, delivering performance enhancements of
  3.9% on the OpenROAD QA benchmark and 8.25% on production-level chip QA b
 enchmarks, surpassing state-of-the-art baselines.\n\nTopics: AI\n\nTracks:
  AI1: AI/ML Algorithms\n\nSession Chairs: You Li (Northwestern University)
  and Biresh Joardar\n\n
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