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DTSTAMP:20260402T024533Z
LOCATION:3001\, Level 3
DTSTART;TZID=America/Los_Angeles:20250624T133000
DTEND;TZID=America/Los_Angeles:20250624T134500
UID:dac_DAC 2025_sess105_RESEARCH2386@linklings.com
SUMMARY:Free and Fair Hardware: A Pathway to Copyright Infringement-Free V
 erilog Generation using LLMs
DESCRIPTION:Samuel Bush, Matthew DeLorenzo, Phat Tieu, and Jeyavijayan Raj
 endran (Texas A&M University)\n\nLimitations in Large Language Model (LLM)
  capabilities for hardware design tasks, such as generating functional Ver
 ilog codes, have motivated various fine-tuning optimizations utilizing cur
 ated hardware datasets from open-source repositories. However, these datas
 ets remain limited in size and contain minimal checks on licensing for reu
 se, resulting in potential copyright violations by fine-tuned LLMs. Theref
 ore, we propose an evaluation benchmark to estimate the risk of Verilog-tr
 ained LLMs to generate copyright-protected codes. To minimize this risk, w
 e present an open-source Verilog dataset, FreeSet, containing over 220k fi
 les, along with the automated dataset curation framework utilized to provi
 de additional guarantees of fair-use Verilog data. We then perform LLM fin
 e-tuning framework consisting of continual pre-training, resulting in a fi
 ne-tuned Llama model for Verilog, FreeV. Our results indicate that FreeV d
 emonstrates the smallest risk of copyright-infringement among prior works,
  with only a 3% violation rate. Furthermore, experimental results demonstr
 ate improvements in Verilog generation functionality over its baseline mod
 el, improving VerilogEval pass@10 rates by over 10%.\n\nTopics: AI\n\nTrac
 ks: AI2: AI/ML Application and Infrastructure\n\nSession Chairs: Luis Guer
 ra e Silva (IST Tecnico / ULisboa, INESC-ID) and Yutaka Masuda (Nagoya Uni
 versity)\n\n
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