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DTSTART:19700308T020000
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DTSTAMP:20260402T024509Z
LOCATION:3001\, Level 3
DTSTART;TZID=America/Los_Angeles:20250623T133000
DTEND;TZID=America/Los_Angeles:20250623T150000
UID:dac_DAC 2025_sess108@linklings.com
SUMMARY:Transformers: Rise of the Optimized Large Language Models
DESCRIPTION:This session is about transformers and large language model op
 timizations. As LLMs are essentially made of transformers due to their sup
 erior effectiveness to understand context and relationships within sequenc
 es by using self-attention mechanism, their hardware optimizations are qui
 te important. We have a best paper award candidate presentation for DRAFT,
  which is about a clever hardware technique that approximates the backprop
 agation hardware for great energy efficiency improvement. Our other papers
  cover hardware/algorithm co-design, retrieval-in-memory techniques, atten
 tion, long-context generation, and an overview of the pareto-frontier for 
 low-precision data formats.\n\nMove Less, Retrieve Fast: A Retrieval-in-Me
 mory Architecture for Language Models\n\nRetrieval-augmented language mode
 ls (RALMs) have attracted widespread attention for addressing the limitati
 ons of traditional large language models. However, challenges involved in 
 retrieval, including substantial data movement and irregular access patter
 ns, seriously impact the efficiency and deplo...\n\n\nJiaxian Chen, Yuxuan
  Qi, Jianan Yuan, Kaoyi Sun, Tianyu Wang, Chenlin Ma, and Yi Wang (Shenzhe
 n University)\n---------------------\nSSFT: Algorithm and Hardware Co-desi
 gn for Structured Sparse Fine-Tuning of Large Language Models\n\nA signifi
 cant number of users depend on Large Language Models (LLMs) for downstream
  tasks, but training LLMs from scratch remains prohibitively expensive. Sp
 arse fine-tuning (SFT) has emerged as an effective strategy to reduce both
  the time and memory requirements of fine-tuning LLMs, achieving accu...\n
 \n\nMiao Yu and Trevor E. Carlson (National University of Singapore)\n----
 -----------------\nAn Energy-Efficient High-Utilization Hardware Architect
 ure for Attention Mechanism in Transformer using Balanced Systolic Array a
 nd Multi-Row Interleaved Operation Ordering\n\nDesigning energy-efficient,
  high-speed accelerators for attention mechanisms, which dominate energy a
 nd latency in Transformers, is increasingly significant. We observe two li
 mitations in previous work: First, existing systolic arrays (SAs) fail to 
 balance data reuse, register saving, and utilizatio...\n\n\nHaiyang Zhou, 
 Hongyang Hu, Jinshan Yue, Hanghang Gao, Yuanlu Xie, Xiaoxin Xu, and Chunme
 ng Dou (Institute of Microelectronics, Chinese Academy of Sciences) and Mi
 ng Liu (Fudan University)\n---------------------\nDRAFT: Decoupling Backpr
 opagation from Pre-trained Backbone for Efficient Transformer Fine-Tuning 
 on Edge\n\nTransformers have demonstrated outstanding performance across d
 iverse applications recently, necessitating fine-tuning to optimize their 
 performance for downstream tasks. However, fine-tuning remains challenging
  due to the substantial computational costs and storage overhead of backpr
 opagation (BP)....\n\n\nZhirui Huang and Shiwei Liu (Fudan University); Ha
 ozhe Zhu and Qi Liu (State Key Lab of Integrated Chips and Systems, Fudan 
 University); and Chixiao Chen (Fudan University)\n---------------------\nK
 VO-LLM: Boosting Long-Context Generation Throughput for Batched LLM Infere
 nce\n\nWith the widespread deployment of long-context large language model
 s (LLMs), efficient and high-quality generation is becoming increasingly i
 mportant. Modern LLMs employ batching and key-value (KV) cache to improve 
 generation throughput and quality. However, as the context length and batc
 h size rise...\n\n\nZhenyu Li, Dongxu Lyu, Gang Wang, Yuzhou Chen, Liyan C
 hen, Wenjie Li, Jianfei Jiang, Yanan Sun, and Guanghui He (Shanghai Jiao T
 ong University)\n---------------------\nFinding the Pareto Frontier of Low
 -Precision Data Formats and MAC Architecture for LLM Inference\n\nTo accel
 erate AI applications, numerous data formats and physical implementations 
 of matrix multiplication have been proposed, creating a complex design spa
 ce.\nThis paper studies the efficient MAC implementation of the integer, f
 loating-point, posit, and logarithmic number system (LNS) data formats ...
 \n\n\nBrian Crafton, Xiaochen Peng, Xiaoyu Sun, Ashwin Lele, and Bo Zhang 
 (TSMC); Win-San Khwa (Taiwan Semiconductor Manufacturing Company); and Ker
 em Akarvardar (TSMC)\n\nTopics: AI\n\nTracks: AI3: AI/ML Architecture Desi
 gn\n\nSession Chairs: Abdelrahman Hosny (Apple Inc.) and Marina Neseem (Nv
 idia)
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