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DTSTAMP:20260402T024534Z
LOCATION:3001\, Level 3
DTSTART;TZID=America/Los_Angeles:20250623T144500
DTEND;TZID=America/Los_Angeles:20250623T150000
UID:dac_DAC 2025_sess108_RESEARCH301@linklings.com
SUMMARY:Finding the Pareto Frontier of Low-Precision Data Formats and MAC 
 Architecture for LLM Inference
DESCRIPTION:Brian Crafton, Xiaochen Peng, Xiaoyu Sun, Ashwin Lele, and Bo 
 Zhang (TSMC); Win-San Khwa (Taiwan Semiconductor Manufacturing Company); a
 nd Kerem Akarvardar (TSMC)\n\nTo accelerate AI applications, numerous data
  formats and physical implementations of matrix multiplication have been p
 roposed, creating a complex design space.\nThis paper studies the efficien
 t MAC implementation of the integer, floating-point, posit, and logarithmi
 c number system (LNS) data formats and Microscaling (MX) and Vector-Scaled
  Quantization (VSQ) block data formats.\nWe evaluate the area, power, and 
 numerical accuracy of >25,000 MAC designs spanning each data format and se
 veral key design parameters.\nWe find that pareto optimal MAC designs with
  emerging data formats (LNS16, MXINT8, VSQINT4) achieve 1.8x, 2.2x, and 1.
 9x TOPS/W improvement compared to FP16, FP8, and FP4 implementations.\n\nT
 opics: AI\n\nTracks: AI3: AI/ML Architecture Design\n\nSession Chairs: Abd
 elrahman Hosny (Apple Inc.) and Marina Neseem (Nvidia)\n\n
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