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DTSTAMP:20260402T024534Z
LOCATION:3001\, Level 3
DTSTART;TZID=America/Los_Angeles:20250623T143000
DTEND;TZID=America/Los_Angeles:20250623T144500
UID:dac_DAC 2025_sess108_RESEARCH490@linklings.com
SUMMARY:An Energy-Efficient High-Utilization Hardware Architecture for Att
 ention Mechanism in Transformer using Balanced Systolic Array and Multi-Ro
 w Interleaved Operation Ordering
DESCRIPTION:Haiyang Zhou, Hongyang Hu, Jinshan Yue, Hanghang Gao, Yuanlu X
 ie, Xiaoxin Xu, and Chunmeng Dou (Institute of Microelectronics, Chinese A
 cademy of Sciences) and Ming Liu (Fudan University)\n\nDesigning energy-ef
 ficient, high-speed accelerators for attention mechanisms, which dominate 
 energy and latency in Transformers, is increasingly significant. We observ
 e two limitations in previous work: First, existing systolic arrays (SAs) 
 fail to balance data reuse, register saving, and utilization. Second, laye
 r-by-layer operation ordering incurs high SRAM access overhead for interme
 diate results. To address the first, we propose the "Balanced Systolic Arr
 ay," improving energy efficiency (EE) by 40% with a 99.5% utilization rate
 . To address the second, we propose "Multi-Row Interleaved" operation orde
 ring, reducing SRAM energy by 31.7%. Combining these techniques, the propo
 sed accelerator improves EE by 39% over previous works.\n\nTopics: AI\n\nT
 racks: AI3: AI/ML Architecture Design\n\nSession Chairs: Abdelrahman Hosny
  (Apple Inc.) and Marina Neseem (Nvidia)\n\n
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