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DTSTAMP:20260402T024532Z
LOCATION:3002\, Level 3
DTSTART;TZID=America/Los_Angeles:20250624T161500
DTEND;TZID=America/Los_Angeles:20250624T163000
UID:dac_DAC 2025_sess117_RESEARCH538@linklings.com
SUMMARY:A Data-Centric Hardware Accelerator for Efficient Adaptive Radix T
 ree
DESCRIPTION:Jin Zhao, Yu Zhang, Jun Huang, weihang yin, Hui Yu, Hao Qi, an
 d Zixiao Wang (Huazhong University of Science and Technology); longlong li
 n (Southwest University); and Xiaofei Liao and Hai Jin (Huazhong Universit
 y of Science and Technology)\n\nThe Adaptive Radix Tree (ART) is a widely 
 used tree index structure prevalent in various domains such as databases a
 nd key-value stores. Despite many solutions have been proposed to improve 
 the performance of ART, they still suffer from significant redundant tree 
 traversals and serious synchronization costs when concurrently performing 
 the operations (e.g., read/write) over ART. In this work, we observe that 
 most operations of real-world workloads tend to target a small subset of A
 RT nodes frequently, exhibiting strong temporal and spatial similarities a
 mong the operations. Based on this observation, we propose a data-centric 
 hardware accelerator, called DCART, to support the operations over ART eff
 iciently. Specifically, DCART proposes a novel data-centric processing mod
 el into the accelerator design to coalesce the operations associated with 
 the same ART nodes and adaptively cache the frequently traversed ART nodes
  and their search results, thereby fully exploiting the similarities among
  the operations for lower tree traversal and synchronization overhead. We 
 implemented DCART on the Xilinx Alveo U280 FPGA card and compared it with 
 the cutting-edge solutions, DCART achieves 21.1×-44.2× speedups and 71.1×-
 148.9× energy savings.\n\nTopics: Design\n\nTracks: DES1: SoC, Heterogeneo
 us, and Reconfigurable Architectures\n\nSession Chairs: Tianhao Cai (Beiha
 ng University) and Dirk Stroobandt (Ghent University)\n\n
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