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DTSTART:19700308T020000
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DTSTART:19701101T020000
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BEGIN:VEVENT
DTSTAMP:20260402T024534Z
LOCATION:3002\, Level 3
DTSTART;TZID=America/Los_Angeles:20250624T160000
DTEND;TZID=America/Los_Angeles:20250624T161500
UID:dac_DAC 2025_sess117_RESEARCH619@linklings.com
SUMMARY:HiSpTRSV: Exploring Tile-Level Parallelism for SpTRSV Acceleration
  on FPGAs
DESCRIPTION:Fan Sun, Fang Dong, and Dian Shen (Southeast University)\n\nSp
 arse Triangular Solve (SpTRSV) is a critical level-2 kernel in sparse Basi
 c Linear Algebra Subprograms (BLAS). While Field-Programmable Gate Array (
 FPGA) accelerators for SpTRSV focus on optimizing individual tiles, they o
 verlook inter-tile parallelism. Designing an inter-tile parallelism accele
 rator poses challenges, including constructing fine-grained dependency gra
 ph, handling communication overhead, and balancing workloads. HiSpTRSV add
 resses these challenges through dependency graph parsing, tile-based highl
 y parallel algorithm, filtering mechanisms, and bidirectional matching wit
 h modular indexing. Experimental show HiSpTRSV outperforms the state-of-th
 e-art SpTRSV accelerator in terms of a 34.3% performance improvement. HiSp
 TRSV achieves a 3.58× speedup and 9.59× higher energy efficiency compared 
 to GPUs.\n\nTopics: Design\n\nTracks: DES1: SoC, Heterogeneous, and Reconf
 igurable Architectures\n\nSession Chairs: Tianhao Cai (Beihang University)
  and Dirk Stroobandt (Ghent University)\n\n
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