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DTSTAMP:20260402T024534Z
LOCATION:3002\, Level 3
DTSTART;TZID=America/Los_Angeles:20250624T170000
DTEND;TZID=America/Los_Angeles:20250624T171500
UID:dac_DAC 2025_sess117_RESEARCH620@linklings.com
SUMMARY:Rewire: Advancing CGRA Mapping Through a Consolidated Routing Para
 digm
DESCRIPTION:Zhaoying Li, Dan Wu, Dhananjaya Wijerathne, Dan Chen, and Huiz
 e Li (National University of Singapore); Cheng Tan (Google); and Tulika Mi
 tra (National University of Singapore)\n\nCoarse-Grained Reconfigurable Ar
 rays (CGRA) balance the performance and power efficiency in computing syst
 ems. Effective compilers play a crucial role in fully realizing its potent
 ial. The compiler maps Data Flow Graphs (DFG), which represent compute-int
 ensive loop kernels, onto CGRAs. However, existing compilers often tackle 
 DFG nodes individually, neglecting their intricate inter-dependencies. We 
 introduce a novel mapping paradigm called Rewire that can place and route 
 multiple nodes in one shot. \nRewire first generates routing information t
 hat is shareable among multiple nodes via propagation. Then, Rewire inters
 ects the routing information to generate individual placement candidates f
 or each node. \nFinally, Rewire innovatively utilizes data dependencies as
  constraints to quickly find suitable placement for multiple nodes togethe
 r. Our evaluation demonstrates that Rewire can generate more near-optimal 
 mappings than prior works. Rewire achieves 2.1x and 1.3x performance impro
 vement and 13.5x and 4.7x compilation time reduction, respectively, compar
 ed to two popular mappers.\n\nTopics: Design\n\nTracks: DES1: SoC, Heterog
 eneous, and Reconfigurable Architectures\n\nSession Chairs: Tianhao Cai (B
 eihang University) and Dirk Stroobandt (Ghent University)\n\n
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