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DTSTAMP:20260402T024533Z
LOCATION:3002\, Level 3
DTSTART;TZID=America/Los_Angeles:20250624T153000
DTEND;TZID=America/Los_Angeles:20250624T154500
UID:dac_DAC 2025_sess117_RESEARCH791@linklings.com
SUMMARY:HeteroSVD: Efficient SVD Accelerator on Versal ACAP with Algorithm
 -Hardware Co-Design
DESCRIPTION:Xinya Luan (Beijing University of Posts and Telecommunications
 ); Zhe Lin (Sun Yat-sen University); and Kai Shi, Jianwang Zhai, and Kang 
 Zhao (Beijing University of Posts and Telecommunications)\n\nSingular valu
 e decomposition (SVD) is a matrix factorization technique widely used in s
 ignal processing and recommendation systems, etc. In general, the time com
 plexity of SVD algorithms is cubic to\nthe problem size, making SVD algori
 thms difficult to meet stringent performance requirements in real-time. Ho
 wever, existing FPGA and GPU solutions fall short of jointly optimizing la
 tency, throughput, and\npower consumption. To settle this issue, this pape
 r proposes HeteroSVD, a heterogeneous reconfigurable accelerator for SVD c
 omputation on the Versal ACAP platform. HeteroSVD introduces a system-leve
 l SVD decomposition mechanism and proposes an algorithm-hardware co-design
 \nmethod to jointly optimize SVD ordering and AI engine (AIE)-centric data
 flow and placement with Versal. Furthermore, in order to improve the quali
 ty of results (QoR) and facilitate micro-architecture selection, we introd
 uce an automatic optimization framework that performs accurate\nperformanc
 e modeling and fast design space exploration. Experiment results demonstra
 te that HeteroSVD reduces the latency by 1.98× over existing FPGA accelera
 tors and outperforms GPU solutions with an improvement of up to 7.22× in l
 atency, 1.77× in throughput, and 13.18× in energy efficiency.\n\nTopics: D
 esign\n\nTracks: DES1: SoC, Heterogeneous, and Reconfigurable Architecture
 s\n\nSession Chairs: Tianhao Cai (Beihang University) and Dirk Stroobandt 
 (Ghent University)\n\n
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