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DTSTART:19700308T020000
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DTSTAMP:20260402T024533Z
LOCATION:3002\, Level 3
DTSTART;TZID=America/Los_Angeles:20250624T171500
DTEND;TZID=America/Los_Angeles:20250624T173000
UID:dac_DAC 2025_sess117_RESEARCH980@linklings.com
SUMMARY:Routability-aware Packing for High-density Nonvolatile FPGAs
DESCRIPTION:Huichuan Zheng, Yuqing Xiong, Jian Zuo, Hao Zhang, Zhenge Jia,
  and Mengying Zhao (Shandong University)\n\nNonvolatile field-programmable
  gate arrays (NVFPGAs) can use multi-level cell (MLC) nonvolatile memories
  (NVMs) to enhance their logic density. However, the high-density design o
 f NVFPGAs degrades the intra-routability of configurable logic blocks (CLB
 s), which significantly prolongs the time consumed by the packing process 
 in the computer-aided design (CAD) flow. To relieve the efficiency degrada
 tion, in this paper, we propose a routability-aware re-pair stage to adjus
 t the logical-physical look-up table (LUT) assignments to mitigate the con
 gestion and improve their intra-routability, thereby reducing the packing 
 time. In addition, exploiting the structural equivalence of MLC LUTs, we r
 emove unnecessary intra-routing attempts from packing to further improve e
 fficiency. Evaluation shows the proposed strategies reduce packing time by
  41.48% on average.\n\nTopics: Design\n\nTracks: DES1: SoC, Heterogeneous,
  and Reconfigurable Architectures\n\nSession Chairs: Tianhao Cai (Beihang 
 University) and Dirk Stroobandt (Ghent University)\n\n
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