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DTSTAMP:20260402T024533Z
LOCATION:3002\, Level 3
DTSTART;TZID=America/Los_Angeles:20250624T164500
DTEND;TZID=America/Los_Angeles:20250624T170000
UID:dac_DAC 2025_sess117_RESEARCH998@linklings.com
SUMMARY:GPS: GNN-Based Two-Stage Pre-Scheduling Loop Mapping Method on CGR
 As
DESCRIPTION:Mingyang Kou and Weiqing Ji (University of Science and Technol
 ogy of China), Shouyi YIN (Tsinghua University), and Hailong Yao (Universi
 ty of Science and Technology of China)\n\nCoarse-grained reconfigurable ar
 chitecture (CGRA) has emerged as a promising solution for accelerating com
 putationally intensive applications, particularly in the field of artifici
 al intelligence. One of the primary challenges for CGRA compilers is gener
 ating effective mapping results for complex applications within a limited 
 timeframe. This paper presents an enhanced pre-scheduling method that inte
 grates Integer Linear Programming (ILP) and Graph Neural Networks (GNN), a
 long with a corresponding two-stage mapping approach. This combination sig
 nificantly reduces the search space and accelerates the solution process f
 or mapping problems. Experimental results demonstrate performance improvem
 ents ranging from 29.4% to 406.7%, along with compilation time reductions 
 of up to 1106.8x compared to existing compilation techniques, as well as e
 xcellent scalability.\n\nTopics: Design\n\nTracks: DES1: SoC, Heterogeneou
 s, and Reconfigurable Architectures\n\nSession Chairs: Tianhao Cai (Beihan
 g University) and Dirk Stroobandt (Ghent University)\n\n
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