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DTSTAMP:20260402T024508Z
LOCATION:3003\, Level 3
DTSTART;TZID=America/Los_Angeles:20250624T153000
DTEND;TZID=America/Los_Angeles:20250624T173000
UID:dac_DAC 2025_sess123@linklings.com
SUMMARY:Breakthroughs in VLSI: Power-Efficient AI and Revolutionary Circui
 try
DESCRIPTION:This session brings together groundbreaking research and innov
 ative advancements in the fields of VLSI design, power efficiency, AI-driv
 en design automation, and advanced circuitry. The goal is to explore and d
 iscuss the latest developments that are pushing the boundaries of technolo
 gy, circuits, and systems.  The session presents topics on DNN accelerator
 s, AI-driven design automation, and innovations in analog circuit design. 
 The session also covers new energy efficient technologies in digital desig
 n, including probabilistic quantum tunneling for robotic perception and mu
 ltifunctional backside metal layers, as well as energy-efficient solutions
  for RISC-V cores and video coding. It provides a comprehensive overview i
 nto the challenges, methodologies, and breakthroughs shaping the future of
  semiconductor technology and electronic design.\n\nTowards Uncertainty-aw
 are Robotic Perception via Mixed-signal BNN Engine Leveraging Probabilisti
 c Quantum Tunneling\n\nIntegrating deep learning with environmental percep
 tion enhances robotic adaptability to complex tasks. However, its ``black-
 box'' nature, such as the lack of uncertainty quantification, poses challe
 nges for safety-critical applications, particularly in unstructured and no
 isy environments. Bayesian ...\n\n\nLikai Pei, Yu Zhou, Xingtian Wang, Xue
 ji Zhao, Wanxin Huang, and Boyang Cheng (University of Notre Dame); Halid 
 Mulaosmanovic, Stefan Duenkel, Dominik Kleimaier, and Sven Beyer (GlobalFo
 undries); and Kai Ni, Mengxue Hou, Michael Niemier, and Ningyuan Cao (Univ
 ersity of Notre Dame)\n---------------------\nEPIC: Error PredIction and C
 orrection for Power-Efficient Voltage Underscaling Multiply-Accumulate Uni
 t\n\nMatrix multiplication dominates the power consumption in compute-inte
 nsive applications such as deep neural networks (DNNs), spurring intensive
  investigations into power-efficient multiply-accumulate (MAC) units. Amon
 g the mainstream low-power design methodologies, voltage underscaling can 
 achieve e...\n\n\nTongjing Wu, Xiaolu Hu, and Tong Li (Shanghai Jiao Tong 
 University); Siting Liu (ShanghaiTech University); and Hui Wang, Weifeng H
 e, Zhigang Mao, and Honglan Jiang (Shanghai Jiao Tong University)\n-------
 --------------\nPoP-ECC: Robust and Flexible Error Correction against Mult
 i-Bit Upsets in DNN Accelerators\n\nDeep Neural Networks (DNNs) in safety-
 critical systems require high reliability. Many systems deploy Error Corre
 ction Codes (ECCs) to protect DNNs from memory errors. However, continuous
  process scaling increases memory errors in severity and frequency, necess
 itating strong protection against Multi-...\n\n\nTaewon Park (Samsung), Sa
 eid Gorgin (Sungkyunkwan University), Dongwhee Kim (Samsung), Jaeho Shin (
 Sungkyunkwan University), Michael Sullivan (Nvidia), and Jungrae Kim (Sung
 kyunkwan University)\n---------------------\nBS-PDN-Last: Towards Optimal 
 Power Delivery Network Design With Multifunctional Backside Metal Layers\n
 \nThe increasing demand to maximize PPA gains with backside metal layers h
 as driven their function beyond power delivery. This study introduces a no
 vel BS-PDN-last flow, crucial for leveraging multifunctional backside meta
 l layers, by deferring power routing to the post-signal routing stage. Thi
 s appr...\n\n\nMin Gyu Park, Amaan Rahman, and Sung Kyu Lim (Georgia Insti
 tute of Technology)\n---------------------\nEVA: An Efficient and Versatil
 e Generative Engine for Targeted Discovery of Novel Analog Circuits\n\nAna
 log circuit design has traditionally depended on manual expertise, slowing
  the discovery of novel topologies essential for advanced technologies lik
 e AI, 5G/6G, and quantum computing. While AI-driven methods have accelerat
 ed hardware design workflows, most of them focus on topology synthesis, of
 t...\n\n\nJian Gao (Northeastern University), Weimin Fu and Xiaolong Guo (
 Kansas State University), Weidong Cao (George Washington University), and 
 Xuan Zhang (Northeastern University)\n---------------------\nA High-Precis
 ion and Low-Cost Approximate Transform Accelerator for Video Coding\n\nThe
  introduction of multiple transform types into the Versatile Video Coding 
 (VVC) standard has yielded notable encoding gains but also imposed conside
 rable computational burdens. Existing transform circuits of different type
 s are typically implemented separately due to their independence, leading 
 t...\n\n\nZhijian Hao (Xidian University); Jiaming Liu, Chenlong He, Qi Zh
 eng, and Shushi Chen (Fudan University); Jinchang Xu (Peking University); 
 Yue Hao (Xidian University); Xiao Yan (Xi'an University of Posts & Telecom
 munications); and Xiaohua Ma (Xidian University)\n---------------------\nA
 dreamDCO: AI-Driven Robust and Efficient Design Automation for Digitally C
 ontrolled Oscillators\n\nThis paper presents how we leverage AI-human coll
 aboration to develop an end-to-end, automated design flow for digitally co
 ntrolled oscillators (DCOs), a key radio-frequency (RF) integrated circuit
 s (ICs) building block that dominates phase noise and jitter performance o
 f RF systems. Specifically, w...\n\n\nYaolong Hu and Hao Guo (Rice Univers
 ity), Shikai Wang (George Washington University), Jiaqi Liu (Rice Universi
 ty), Weidong Cao (George Washington University), and Taiyun Chi (Rice Univ
 ersity)\n---------------------\nDual-Issue Execution of Mixed Integer and 
 Floating-Point Workloads on Energy-Efficient In-Order RISC-V Cores\n\nTo m
 eet the computational requirements of modern workloads under tight energy 
 constraints, general-purpose accelerator architectures have to integrate a
 n ever-increasing number of extremely area- and energy-efficient processin
 g elements (PEs).\nIn this context, single-issue in-order cores are common
 p...\n\n\nLuca Colagrande (ETH Zürich) and Luca Benini (Università di Bolo
 gna)\n\nTopics: Design\n\nTracks: DES4: Digital and Analog Circuits\n\nSes
 sion Chairs: Ioannis Savidis (Drexel University) and Kishor Kunal (Nvidia)
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