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DTSTART;TZID=America/Los_Angeles:20250624T153000
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UID:dac_DAC 2025_sess123_RESEARCH1510@linklings.com
SUMMARY:EPIC: Error PredIction and Correction for Power-Efficient Voltage 
 Underscaling Multiply-Accumulate Unit
DESCRIPTION:Tongjing Wu, Xiaolu Hu, and Tong Li (Shanghai Jiao Tong Univer
 sity); Siting Liu (ShanghaiTech University); and Hui Wang, Weifeng He, Zhi
 gang Mao, and Honglan Jiang (Shanghai Jiao Tong University)\n\nMatrix mult
 iplication dominates the power consumption in compute-intensive applicatio
 ns such as deep neural networks (DNNs), spurring intensive investigations 
 into power-efficient multiply-accumulate (MAC) units. Among the mainstream
  low-power design methodologies, voltage underscaling can achieve effectiv
 e power savings yet induce timing errors that may lead to catastrophic acc
 uracy loss. In this paper, we propose an error prediction and correction f
 ramework (denoted as EPIC) for arbitrary MAC unit under voltage underscali
 ng, which predicts the timing errors and samples the correct output by usi
 ng a delay-tunable clock. A prediction bits searching algorithm is propose
 d to enhance the prediction accuracy with low hardware cost, resulting in 
 up to 100% accuracy. While preserving the accuracy, EPIC achieves up to 52
 % power savings over the corresponding MAC operating at nominal voltage. W
 ith transistor-level optimizations, EPIC incurs only 8% area and 1% power 
 overheads, achieving 100% error correction under a voltage underscaling ra
 tio of 0.74. Compared to state-of-the-art error resilient circuit designs,
  EPIC consumes 60%-88% less area. Additionally, to achieve the accuracy pe
 rformance of EPIC in error-resilient applications, we propose a simulation
  workflow involving precise timing features, enabling an accurate simulati
 on of voltage underscaling MAC in large-scale applications. The experiment
 al results show that, under voltage-underscaling, the MAC with EPIC consum
 es 11% less power than the one without EPIC, when a same accuracy as exact
  implementation is required in multi-layer perceptron (MLP).\n\nTopics: De
 sign\n\nTracks: DES4: Digital and Analog Circuits\n\nSession Chairs: Ioann
 is Savidis (Drexel University) and Kishor Kunal (Nvidia)\n\n
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