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DTSTART:19700308T020000
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DTSTAMP:20260402T024532Z
LOCATION:3003\, Level 3
DTSTART;TZID=America/Los_Angeles:20250624T154500
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UID:dac_DAC 2025_sess123_RESEARCH1636@linklings.com
SUMMARY:PoP-ECC: Robust and Flexible Error Correction against Multi-Bit Up
 sets in DNN Accelerators
DESCRIPTION:Taewon Park (Samsung), Saeid Gorgin (Sungkyunkwan University),
  Dongwhee Kim (Samsung), Jaeho Shin (Sungkyunkwan University), Michael Sul
 livan (Nvidia), and Jungrae Kim (Sungkyunkwan University)\n\nDeep Neural N
 etworks (DNNs) in safety-critical systems require high reliability. Many s
 ystems deploy Error Correction Codes (ECCs) to protect DNNs from memory er
 rors. However, continuous process scaling increases memory errors in sever
 ity and frequency, necessitating strong protection against Multi-Bit Upset
 s (MBUs). This paper proposes Parities of Parities ECC (PoP-ECC), a novel 
 two-tier memory protection scheme designed to provide robust, efficient, a
 nd flexible protection against MBUs. PoP-ECC generates Virtual Parities (V
 Ps), which are used to compute second-level parities called Parities of Pa
 rities (PPs). This two-level ECC structure allows for dynamic error correc
 tion tailored to varying error patterns, ensuring system reliability with 
 minimal memory overhead. Our evaluation demonstrates that PoP-ECC can tole
 rate significantly higher MBU ratios compared to state-of-the-art solution
 s, with negligible delay, area, and power overhead.\n\nTopics: Design\n\nT
 racks: DES4: Digital and Analog Circuits\n\nSession Chairs: Ioannis Savidi
 s (Drexel University) and Kishor Kunal (Nvidia)\n\n
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