BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260402T024533Z
LOCATION:3003\, Level 3
DTSTART;TZID=America/Los_Angeles:20250624T171500
DTEND;TZID=America/Los_Angeles:20250624T173000
UID:dac_DAC 2025_sess123_RESEARCH815@linklings.com
SUMMARY:A High-Precision and Low-Cost Approximate Transform Accelerator fo
 r Video Coding
DESCRIPTION:Zhijian Hao (Xidian University); Jiaming Liu, Chenlong He, Qi 
 Zheng, and Shushi Chen (Fudan University); Jinchang Xu (Peking University)
 ; Yue Hao (Xidian University); Xiao Yan (Xi'an University of Posts & Telec
 ommunications); and Xiaohua Ma (Xidian University)\n\nThe introduction of 
 multiple transform types into the Versatile Video Coding (VVC) standard ha
 s yielded notable encoding gains but also imposed considerable computation
 al burdens. Existing transform circuits of different types are typically i
 mplemented separately due to their independence, leading to substantial ha
 rdware overhead. To address this, we explore the relationship between Disc
 rete Cosine Transform Type-2 (DCT2) and Discrete Sine Transform Type-7 (DS
 T7) matrices and reveal a prominent diagonal aggregation phenomenon in the
  elements of the transfer matrix. Based on this insight, the least-squares
  method is applied to optimize the transfer matrix sparsity, achieving a h
 igh-precision, low-cost approximate conversion from DCT2 to DST7. Furtherm
 ore, we optimize DCT2 computation by proposing an elaborate matrix decompo
 sition approach that allows a lightweight shift-adder unit to efficiently 
 generate all required product terms across varying sizes. Leveraging these
  algorithmic optimizations, we implement a highly reusable and area-effici
 ent approximate transform accelerator that supports sizes from 4 to 32 poi
 nts and accommodates three types in VVC. Experimental results demonstrate 
 that the proposed accelerator achieves over 44% reduction in circuit resou
 rce consumption with minimal BD-BR performance loss of just 0.57%, maintai
 ning processing capabilities up to 8K@57 fps.\n\nTopics: Design\n\nTracks:
  DES4: Digital and Analog Circuits\n\nSession Chairs: Ioannis Savidis (Dre
 xel University) and Kishor Kunal (Nvidia)\n\n
END:VEVENT
END:VCALENDAR