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DTSTAMP:20260402T024534Z
LOCATION:3003\, Level 3
DTSTART;TZID=America/Los_Angeles:20250624T170000
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UID:dac_DAC 2025_sess123_RESEARCH864@linklings.com
SUMMARY:Dual-Issue Execution of Mixed Integer and Floating-Point Workloads
  on Energy-Efficient In-Order RISC-V Cores
DESCRIPTION:Luca Colagrande (ETH Zürich) and Luca Benini (Università di Bo
 logna)\n\nTo meet the computational requirements of modern workloads under
  tight energy constraints, general-purpose accelerator architectures have 
 to integrate an ever-increasing number of extremely area- and energy-effic
 ient processing elements (PEs).\nIn this context, single-issue in-order co
 res are commonplace, but lean dual-issue cores could boost PE IPC, especia
 lly for the common case of mixed integer and floating-point workloads.\nWe
  develop the COPIFT methodology and RISC-V ISA extensions to enable low-co
 st and flexible dual-issue execution of mixed integer and floating-point i
 nstruction sequences. On such kernels, our methodology achieves speedups o
 f 1.47x, reaching a peak 1.75 instructions per cycle, and 1.37x energy imp
 rovements on average, over optimized RV32G baselines.\n\nTopics: Design\n\
 nTracks: DES4: Digital and Analog Circuits\n\nSession Chairs: Ioannis Savi
 dis (Drexel University) and Kishor Kunal (Nvidia)\n\n
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