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DTSTAMP:20260402T024533Z
LOCATION:3004\, Level 3
DTSTART;TZID=America/Los_Angeles:20250624T153000
DTEND;TZID=America/Los_Angeles:20250624T154500
UID:dac_DAC 2025_sess128_RESEARCH1553@linklings.com
SUMMARY:Gem5-AcceSys: Enabling System-Level Exploration of Standard Interc
 onnects for Novel Accelerators
DESCRIPTION:Qunyou Liu (École Polytechnique Fédérale de Lausanne), Marina 
 Zapater (HES-SO University of Applied Sciences and Arts Western Switzerlan
 d), and David Atienza (École Polytechnique Fédérale de Lausanne)\n\nThe gr
 owing demand for efficient, high-performance processing in machine learnin
 g (ML) and image processing has made hardware accelerators, such as GPUs a
 nd Data Streaming Accelerators (DSAs), increasingly essential. These accel
 erators enhance ML and image processing tasks by offloading computation fr
 om the CPU to dedicated hardware. These accelerators rely on interconnects
  for efficient data transfer, making interconnect design crucial for syste
 m-level performance. This paper introduces Gem5-AcceSys, an innovative fra
 mework for system-level exploration of standard interconnects and configur
 able memory hierarchies. Using a matrix multiplication accelerator tailore
 d for transformer workloads as a case study, we evaluate PCIe performance 
 across diverse memory types (DDR4, DDR5, GDDR6, HBM2) and configurations, 
 including host-side and device-side memory. Our findings demonstrate that 
 optimized interconnects can achieve up to 80\% of device-side memory perfo
 rmance and, in some scenarios, even surpass it. These results offer action
 able insights for system architects, enabling a balanced approach to perfo
 rmance and cost in next-generation accelerator design.\n\nTopics: EDA\n\nT
 racks: EDA1: Design Methodologies for System-on-Chip and 3D/2.5D System-in
  Package\n\nSession Chairs: Giuseppe Di Guglielmo (Fermilab) and T V Naray
 anan (Ansys)\n\n
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