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DTSTAMP:20260402T024534Z
LOCATION:3004\, Level 3
DTSTART;TZID=America/Los_Angeles:20250624T160000
DTEND;TZID=America/Los_Angeles:20250624T161500
UID:dac_DAC 2025_sess128_RESEARCH2574@linklings.com
SUMMARY:Automated Generation of Decoders for Irregular Instruction Sets Us
 ing Information-Theoretic Decision Trees Construction Algorithms
DESCRIPTION:Lillian Tadros (Technische Universität Dortmund)\n\nInstructio
 n decoders are indispensable components of the System-on-Chip design flow 
 and major constituents of instruction set simulators and processor toolcha
 ins. The complex and lengthy process of manual decoder design can be great
 ly alleviated by automated decoder generation tools based on high level in
 struction definitions. Unfortunately, automatic generation is challenged b
 y the rising complexity of instruction sets as well as irregularities such
  as non-uniform opcodes, logic propositions on bit fields and multiple or 
 nested specializations. The few available state-of-the-art decoder generat
 ion tools either cannot handle irregularities altogether or produce inadeq
 uate results, either functionally or w.r.t. performance. Moreover, they ar
 e largely ad hoc and do not bear on any of the well-established work on de
 cision tree generation.\nThis paper presents a sophisticated decision-tree
  algorithm for the problem of generating decoders for irregular instructio
 n sets. Our algorithm has produced fully automated, functionally correct a
 nd cost-aware decoders for the SPARC, MIPS32 and ARMv7 instruction sets. O
 ur results prove the application of information-theoretic concepts to deco
 der generation a most promising approach.\n\nTopics: EDA\n\nTracks: EDA1: 
 Design Methodologies for System-on-Chip and 3D/2.5D System-in Package\n\nS
 ession Chairs: Giuseppe Di Guglielmo (Fermilab) and T V Narayanan (Ansys)\
 n\n
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