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UID:dac_DAC 2025_sess130_RESEARCH107@linklings.com
SUMMARY:Parallel Dynamic Partitioning for Datapath Combinational Equivalen
 ce Checking
DESCRIPTION:Shuai Zhou and Weikang Zhang (Institute of Computing Technolog
 y, Chinese Academy of Sciences); Xindi Zhang (Institute of Software, Chine
 se Academy of Sciences); Zite Jiang and Haihang You (Institute of Computin
 g Technology, Chinese Academy of Sciences); and Shaowei Cai (Institute of 
 Software, Chinese Academy of Sciences)\n\nCombinational Equivalence Checki
 ng (CEC) is a crucial technique in electronic design automation for verify
 ing the functional equivalence of combinational circuits. Recently, combin
 ational circuit design increasingly incorporates more complex arithmetic s
 tructures, commonly known as datapath circuits. However, existing state-of
 -the-art tools often exhibit subpar performance in solving datapath CEC pr
 oblems. To further advance the exploration on datapath CEC process, this s
 tudy introduces PDP-CEC (Parallel Dynamic Partitioning Combinational Equiv
 alence Checking), a novel parallel CEC approach integrating circuit partit
 ioning and dynamic task scheduling into the CEC process, enhancing the eff
 iciency of CEC for datapath circuits. PDP-CEC introduces an innovative met
 hod for selecting critical nodes to split the search space of the CEC prob
 lem, facilitating the efficient generation of numerous independent subprob
 lems. Meanwhile, a dynamic task scheduling strategy is implemented in PDP-
 CEC to ensure load balancing and prevent hard-to-solve subproblems from st
 alling the entire process. Compared to the most advanced tools such as ABC
  and Hybrid-CEC, PDP-CEC significantly accelerates CEC process, achieving 
 speedups ranging from 5.11x to 125.27x, while effectively solving approxim
 ately three times more datapath CEC problems. With excellent scalability, 
 PDP-CEC shows substantial improvements in combinational equivalence checki
 ng for datapath circuits, offering an efficient parallel approach to meet 
 the demands of large-scale datapath CEC tasks.\n\nTopics: EDA\n\nTracks: E
 DA2: Design Verification and Validation\n\nSession Chairs: Chung-Yang Ric 
 Huang (National Taiwan University) and Nan Wu (George Washington Universit
 y)\n\n
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