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DTSTAMP:20260402T024534Z
LOCATION:3003\, Level 3
DTSTART;TZID=America/Los_Angeles:20250625T161500
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UID:dac_DAC 2025_sess130_RESEARCH2157@linklings.com
SUMMARY:Insights from Rights and Wrongs: A Large Language Model for Solvin
 g Assertion Failures in RTL Design
DESCRIPTION:Jie Zhou (Southeast University), Youshu Ji (National Center of
  Technology Innovation for Electronic Design Automation), Ning Wang (City 
 University of Hong Kong), Yuchen Hu and Xinyao Jiao (Southeast University)
 , Bingkun Yao (City University of Hong Kong), Xinwei Fang (University of Y
 ork), Nan Guan (City University of Hong Kong), Shuai Zhao (Sun Yat-sen Uni
 versity), and Zhe Jiang (Southeast University)\n\nSystemVerilog Assertions
  (SVAs) are essential for verifying Register Transfer Level (RTL) designs,
  as they can be embedded into key functional paths to detect unintended be
 haviours. During simulation, assertion failures occur when the design's be
 haviour deviates from expectations. Solving these failures, i.e., identify
 ing and fixing the issues causing the deviation, requires analysing comple
 x logical and timing relationships between multiple signals. This process 
 heavily relies on human expertise, and there is currently no automatic too
 l available to assist with it. Here, we present AssertSolver, an open-sour
 ce Large Language Model (LLM) specifically designed for solving assertion 
 failures. By leveraging synthetic training data and learning from error re
 sponses to challenging cases, \nAssertSolver achieves a bug-fixing pass@1 
 metric of 88.54% on our testbench, significantly outperforming OpenAI's o1
 -preview by up to 11.97%. We release our model and testbench for public ac
 cess to encourage further research: https://anonymous.4open.science/r/Asse
 rtSolver-9022.\n\nTopics: EDA\n\nTracks: EDA2: Design Verification and Val
 idation\n\nSession Chairs: Chung-Yang Ric Huang (National Taiwan Universit
 y) and Nan Wu (George Washington University)\n\n
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