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DTSTAMP:20260402T024534Z
LOCATION:3003\, Level 3
DTSTART;TZID=America/Los_Angeles:20250625T160000
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UID:dac_DAC 2025_sess130_RESEARCH743@linklings.com
SUMMARY:SIMAX: Accelerating RTL Simulation for Large-Scale Design
DESCRIPTION:Lu Chen (Institute of Computing Technology, Chinese Academy of
  Sciences); Dingyi Zhao (Beijing Institute of Open Source Chip); and Zihao
  Yu, Ninghui Sun, and Yungang Bao (Institute of Computing Technology, Chin
 ese Academy of Sciences)\n\nRegister Transfer Level (RTL) simulation is a 
 crucial tool in hardware design, widely used in design space exploration, 
 verification, debugging, and preliminary performance evaluation. Among var
 ious RTL simulation approaches, software simulation is the most commonly u
 sed due to its flexibility, low cost, and ease of debugging. However, the 
 slow speed of simulation has become the bottleneck in verification, due to
  the extensive overhead required to simulate complex designs.\nIn this wor
 k, we explore the core of RTL simulation and divide it into four stages. F
 or each stage, we propose several techniques to improve the performance. F
 inally, we implement these techniques in a novel RTL simulator SIMAX. SIMA
 X succeeds to simulate XiangShan, the state-of-the-art open-source RISC-V 
 processor. Besides, compared to Verilator, SIMAX can achieve speedup of 7.
 34x for booting Linux in XiangShan, and 19.94x for running CoreMark in Roc
 ketChip.\n\nTopics: EDA\n\nTracks: EDA2: Design Verification and Validatio
 n\n\nSession Chairs: Chung-Yang Ric Huang (National Taiwan University) and
  Nan Wu (George Washington University)\n\n
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