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DTSTAMP:20260402T024533Z
LOCATION:3001\, Level 3
DTSTART;TZID=America/Los_Angeles:20250625T170000
DTEND;TZID=America/Los_Angeles:20250625T171500
UID:dac_DAC 2025_sess132_RESEARCH829@linklings.com
SUMMARY:Near-Memory LLM Inference Processor based on 3D DRAM-to-logic Hybr
 id Bonding
DESCRIPTION:Sanghyeok Han, Yoon Byungkuk, and Gyeonghwan Park (Seoul Natio
 nal University); Choungki Song and Dongkyun Kim (SK hynix); and Jae-Joon K
 im (Seoul National University)\n\nLarge language model (LLM) inference pos
 es dual challenges, demanding substantial memory bandwidth and computing r
 esources. Recent advancements in near-memory accelerators leveraging 3D DR
 AM-to-logic hybrid-bonding (HB) interconnects have gained attention due to
  their highly parallel data transfer capabilities. We address limitations 
 in previous HB-DRAM accelerators, such as those stemming from distributed 
 controller designs, by introducing an architecture with a centralized cont
 roller and dual-IO scheme. This approach not only reduces the chip area ov
 erhead but also enables reconfigurable GEMV/GEMM operations, boosting the 
 performance. Simulations for the OPT 66B model show that our proposed acce
 lerator achieves 2.9X, 3.5X, and 2.5X higher performance compared to NPU, 
 DRAM-PIM, and heterogeneous designs (DRAM-PIM + NPU), respectively.\n\nTop
 ics: Design\n\nTracks: DES2B: In-memory and Near-memory Computing Architec
 tures, Applications and Systems\n\nSession Chairs: Steve Dai (NVIDIA) and 
 Haitong Li (Purdue University)\n\n
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