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BEGIN:VEVENT
DTSTAMP:20260402T024534Z
LOCATION:3001\, Level 3
DTSTART;TZID=America/Los_Angeles:20250625T160000
DTEND;TZID=America/Los_Angeles:20250625T161500
UID:dac_DAC 2025_sess132_RESEARCH967@linklings.com
SUMMARY:SplitSync: Bank Group-Level Split-Synchronization for High-Perform
 ance DRAM PIM
DESCRIPTION:Yoon Byungkuk, Sanghyeok Han, Gyeonghwan Park, and Jae-Joon Ki
 m (Seoul National University)\n\nProcessing in Memory (PIM) architectures 
 enhance memory bandwidth by utilizing bank-level parallelism, typically im
 plemented with a SIMD structure where all banks operate simultaneously und
 er a single command. \nHowever, this synchronous approach requires the act
 ivation of all banks before computation, leading to activation times that 
 exceed computation times, limiting performance gain.\nRecently, asynchrono
 us execution PIM has been proposed as an alternative, allowing banks to op
 erate asynchronously and overlap activation with processing to hide the ro
 w activation overhead. While effective at reducing row activation overhead
 , the independent operation requires large shared accumulators for each ba
 nk group, increasing area overhead. \nTo address the issues, we propose ba
 nk group (BG)-level split synchronization DRAM PIM, where each bank group 
 operates asynchronously to hide row activation overhead while operating sy
 nchronously within the bank group to eliminate the need for shared accumul
 ators. Evaluation results show that our proposed design achieves an averag
 e throughput improvement of 1.70x and 1.06x compared to conventional PIM a
 nd asynchronous execution PIM. \nFurthermore, the area overhead per proces
 sing unit (PU) increases by only 1.5% compared to conventional PIM and is 
 significantly lower than that of asynchronous execution PIM.\n\nTopics: De
 sign\n\nTracks: DES2B: In-memory and Near-memory Computing Architectures, 
 Applications and Systems\n\nSession Chairs: Steve Dai (NVIDIA) and Haitong
  Li (Purdue University)\n\n
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